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ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 1 ? 2006?2010 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. powerpc is a trademark of ibm corp. and is used under li cense. pci, pci express, pcie, and pci-x are trademarks of pc i-sig. all other trademarks are the property of their respective owners. virtex-5 fpga electrical characteristics virtex?-5 fpgas are available in -3, -2, -1 speed grades, with -3 having the highest performance. virtex-5 fpga dc and ac characteristics are specified for both commercial and industrial grades. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this virtex-5 fpga data sheet, part of an overall set of documentation on the virtex-5 family of fpgas, is available on the xilinx website: ? virtex-5 family overview ? virtex-5 fpga user guide ? virtex-5 fpga configuration guide ? virtex-5 fpga xtremedsp? design considerations ? virtex-5 fpga packaging and pinout specification ? embedded processor block in virtex-5 fpgas reference guide ? virtex-5 fpga rocketio? gtp transceiver user guide ? virtex-5 fpga rocketio gtx transceiver user guide ? virtex-5 fpga embedded tri-mode ethernet mac user guide ? virtex-5 fpga integrated endpoint block user guide for pci express? designs ? virtex-5 fpga system monitor user guide ? virtex-5 fpga pcb designer?s guide all specifications are subject to change without notice. virtex-5 fpga dc characteristics 0 virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 00 product specification ta bl e 1 : absolute maximum ratings symbol description units v ccint internal supply voltage relative to gnd ?0.5 to 1.1 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.75 v v batt key memory battery backup supply ?0.5 to 4.05 v v ref input reference voltage ?0.5 to 3.75 v v in (3) 3.3v i/o input voltage relative to gnd (4) (user and dedicated i/os) ?0.75 to 4.05 v 3.3v i/o input voltage relative to gnd (restricted to maximum of 100 user i/os) (5) ?0.95 to 4.4 (commercial temperature) v ?0.85 to 4.3 (industrial temperature) 2.5v or below i/o input voltage relative to gnd (user and dedicated i/os) ?0.75 to v cco + 0.5 v i in current applied to an i/o pin, powered or unpowered 100 ma total current applied to all i/o pins, powered or unpowered 100 ma v ts voltage applied to 3-state 3.3v output (4) (user and dedicated i/os) ?0.75 to 4.05 v voltage applied to 3-state 2.5v or below output (user and dedicated i/os) ?0.75 to v cco + 0.5 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (2) + 220 c t j maximum junction temperature (2) + 125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rating s only, and functional operation of the device at thes e or any other conditions beyond those list ed under operating conditions is not impli ed. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. for soldering guidelines, refer to ug112 : device package user guide . for thermal considerations, refer to ug195 : virtex-5 fpga packaging and pinout specification on the xilinx website. 3. 3.3v i/o absolute maximum limi t applied to dc and ac signals. 4. for 3.3v i/o operation, refer to ug190 : virtex-5 fpga user guide, chapt er 6, 3.3v i/o design guidelines . 5. for more flexibility in specific designs, a maximum of 100 user i/os can be stressed beyond the normal specification for no mor e than 20% of a data period .
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 2 ta bl e 2 : recommended operating conditions symbol description temperature range min max units v ccint internal supply voltage relative to gnd, t j =0 c to +85 c commercial 0.95 1.05 v internal supply voltage relative to gnd, t j = ?40 c to +100 c industrial 0.95 1.05 v v ccaux (1) auxiliary supply voltage relative to gnd, t j =0 c to +85 c commercial 2.375 2.625 v auxiliary supply voltage relative to gnd, t j =?40 c to +100 c industrial 2.375 2.625 v v cco (2,4,5) supply voltage relative to gnd, t j =0 c to +85 c commercial 1.14 3.45 v supply voltage relative to gnd, t j =?40 c to +100 c industrial 1.14 3.45 v v in 3.3v supply voltage relative to gnd, t j =0 c to +85 c commercial gnd ? 0.20 3.45 v 3.3v supply voltage relative to gnd, t j = ?40 c to +100 c industrial gnd ? 0.20 3.45 v 2.5v and below supply voltage relative to gnd, t j =0 c to +85 c commercial gnd ? 0.20 v cco + 0.2 v 2.5v and below supply voltage relative to gnd, t j = ?40 c to +100 c industrial gnd ? 0.20 v cco + 0.2 v i in (6) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode commercial 10 ma industrial 10 ma v batt (3) battery voltage relative to gnd, t j =0 c to +85 c commercial 1.0 3.6 v battery voltage relative to gnd, t j =?40 c to +100 c industrial 1.0 3.6 v notes: 1. recommended maximum voltage drop for v ccaux is 10 mv/ms. 2. configuration data is retained even if v cco drops to 0v. 3. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . 4. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v. 5. the configuration supply voltage v cc_config is also known as v cco_0 . 6. a total of 100 ma per bank should not be exceeded. ta bl e 3 : dc characteristics over recommended operating conditions symbol description data rate min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 v i ref v ref leakage current per pin 10 a i l input or output leakage current per pin (sample-tested) 10 a c in input capacitance (sample-tested) 8pf i rpu (1) pad pull-up (when selected) @ v in =0v, v cco =3.3v 20 150 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 10 90 a pad pull-up (when selected) @ v in =0v, v cco = 1.8v 5 45 a pad pull-up (when selected) @ v in =0v, v cco = 1.5v 3 30 a pad pull-up (when selected) @ v in =0v, v cco = 1.2v 2 15 a i rpd (1) pad pull-down (when selected) @ v in =2.5v 5 110 a i batt (2) battery supply current 150 na n temperature diode ideality factor 1.0002 n r series resistance 5.0 notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum value specified for worst case process at 25c.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 3 important note typical values for quiescent supply current are now spec ified at nominal voltage, 85c junction temperatures (t j ). xilinx recommends analyzing static power consumption at t j = 85c because the majority of designs operate near the high end of the commercial temperature range. data sheets for older produc ts (e.g., virtex-4 devices) st ill specify typical quiescent supply current at t j = 25c. quiescent supply current is specified by speed grade for virtex-5 devices. use the xpower? estimator (xpe) spreadsh eet tool (download at http://www.xilinx.com/power ) to calculate static power consumption for conditions other than those specified in ta bl e 4 . ta bl e 4 : typical quiescent supply current symbol description device speed and temperature grade units -3 (c) -2 (c & i) -1 (c & i) i ccintq quiescent v ccint supply current xc5vlx20t n/a 406 253 ma xc5vlx30 480 480 300 ma xc5vlx30t 507 507 317 ma xc5vlx50 651 651 449 ma xc5vlx50t 689 689 475 ma xc5vlx85 1072 1072 833 ma xc5vlx85t 1115 1115 866 ma XC5VLX110 1391 1391 1109 ma XC5VLX110t 1448 1448 1154 ma xc5vlx155 2615 2615 2141 ma xc5vlx155t 2674 2674 2188 ma xc5vlx220 n/a 2783 2278 ma xc5vlx220t n/a 2844 2328 ma xc5vlx330 n/a 4193 3432 ma xc5vlx330t n/a 4267 3492 ma xc5vsx35t 720 720 554 ma xc5vsx50t 1092 1092 840 ma xc5vsx95t n/a 1924 1475 ma xc5vsx240t n/a 4137 3168 ma xc5vtx150t n/a 2067 2067 ma xc5vtx240t n/a 2881 2881 ma xc5vfx30t 1024 1024 1024 ma xc5vfx70t 1658 1658 1658 ma xc5vfx100t 2875 2875 2875 ma xc5vfx130t 3041 3041 3041 ma xc5vfx200t n/a 3755 3755 ma
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 4 i ccoq quiescent v cco supply current xc5vlx20t n/a 2 2 ma xc5vlx30 1.5 1.5 1.5 ma xc5vlx30t 1.5 1.5 1.5 ma xc5vlx50 2 2 2 ma xc5vlx50t 2 2 2 ma xc5vlx85 3 3 3 ma xc5vlx85t 3 3 3 ma XC5VLX110 4 4 4 ma XC5VLX110t 4 4 4 ma xc5vlx155 8 8 8 ma xc5vlx155t 8 8 8 ma xc5vlx220 n/a 8 8 ma xc5vlx220t n/a 8 8 ma xc5vlx330 n/a 12 12 ma xc5vlx330t n/a 12 12 ma xc5vsx35t 1.5 1.5 1.5 ma xc5vsx50t 2 2 2 ma xc5vsx95t n/a 4 4 ma xc5vsx240t n/a 12 12 ma xc5vtx150t n/a 7 7 ma xc5vtx240t n/a 7 7 ma xc5vfx30t 4 4 4 ma xc5vfx70t 6 6 6 ma xc5vfx100t 7 7 7 ma xc5vfx130t 8 8 8 ma xc5vfx200t n/a 10 10 ma ta bl e 4 : typical quiescent supply current (cont?d) symbol description device speed and temperature grade units -3 (c) -2 (c & i) -1 (c & i)
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 5 i ccauxq quiescent v ccaux supply current xc5vlx20t n/a 32 32 ma xc5vlx30 38 38 38 ma xc5vlx30t 43 43 43 ma xc5vlx50 57 57 57 ma xc5vlx50t 62 62 62 ma xc5vlx85 93 93 93 ma xc5vlx85t 98 98 98 ma XC5VLX110 125 125 125 ma XC5VLX110t 130 130 130 ma xc5vlx155 172 172 172 ma xc5vlx155t 177 177 177 ma xc5vlx220 n/a 229 229 ma xc5vlx220t n/a 236 236 ma xc5vlx330 n/a 345 345 ma xc5vlx330t n/a 353 353 ma xc5vsx35t 49 49 49 ma xc5vsx50t 74 74 74 ma xc5vsx95t n/a 131 131 ma xc5vsx240t n/a 300 300 ma xc5vtx150t n/a 180 180 ma xc5vtx240t n/a 300 300 ma xc5vfx30t606060ma xc5vfx70t 110 110 110 ma xc5vfx100t 150 150 150 ma xc5vfx130t 180 180 180 ma xc5vfx200t n/a 250 250 ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (tj). industrial (i) grade devices have the same typical values as commercial (c) grade devices at 85c, but higher values at 100c. use the xpe tool to calculate 100c values. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the xpower estim ator (xpe) or xpower analyzer (xpa) tools. ta bl e 4 : typical quiescent supply current (cont?d) symbol description device speed and temperature grade units -3 (c) -2 (c & i) -1 (c & i)
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 6 power-on power supply requirements xilinx? fpgas require a certai n amount of supply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. the power supplies can be turned on in any sequence, though the specifications shown in ta b l e 5 are for the recommended power-on sequence of v ccint , v ccaux , and v cco . the i/o will remain 3-stated through power-on if the recommended power-on sequence is followed. xilinx does not specify the current or i/o behavior for other power-on sequences. ta bl e 5 shows the minimum current required by virtex-5 devices for proper power-on and configuration. if the current minimums shown in ta b l e 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. the fpga must be configured after v ccint is applied. once initialized and configured, use the xpower tools to estimate current drain on these supplies. ta bl e 5 : power-on current for virtex-5 devices device i ccintmin i ccauxmin i ccomin units typ (1) typ (1) typ (1) xc5vlx20t 172 54 50 ma xc5vlx30 235 76 50 ma xc5vlx30t 246 86 50 ma xc5vlx50 320 114 50 ma xc5vlx50t 336 124 50 ma xc5vlx85 492 186 100 ma xc5vlx85t 515 196 100 ma XC5VLX110 623 250 100 ma XC5VLX110t 651 260 100 ma xc5vlx155 695 351 100 ma xc5vlx155t 728 368 100 ma xc5vlx220 1023 458 150 ma xc5vlx220t 1056 472 150 ma xc5vlx330 1470 690 150 ma xc5vlx330t 1509 706 150 ma xc5vsx35t 307 98 50 ma xc5vsx50t 472 148 50 ma xc5vsx95t 804 262 100 ma xc5vsx240t 1632 662 150 ma xc5vtx150t 969 386 150 ma xc5vtx240t 1245 572 150 ma xc5vfx30t 358 116 50 ma xc5vfx70t 695 232 100 ma xc5vfx100t 749 298 100 ma xc5vfx130t 1111 392 150 ma xc5vfx200t 1222 534 150 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. the maximum startup current can be obtained using the xpower estimator (xpe) or xpower analyzer (xpa) tools and adding the quiescent plus dynamic current consumption. ta b l e 5 : power-on current for virtex-5 devices device i ccintmin i ccauxmin i ccomin units typ (1) typ (1) typ (1) ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage relative to gnd 0.20 to 50.0 ms
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 7 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : selectio dc input and output levels i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl ?0.3 0.8 2.0 3.45 0.4 2.4 note(3) note(3) lvcmos33, lvdci33 ?0.3 0.8 2.0 3.45 0.4 v cco ? 0.4 note(3) note(3) lvcmos25, lvdci25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note(3) note(3) lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco + 0.3 0.45 v cco ? 0.45 note(4) note(4) lvcmos15, lvdci15 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(4) note(4) lvcmos12 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(6) note(6) pci33_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco note(5) note(5) pci66_3 (5) ?0.2 30% v cco 50% v cco v cco 10% v cco 90% v cco note(5) note(5) pci-x (5) ?0.2 35% v cco 50% v cco v cco 10% v cco 90% v cco note(5) note(5) gtlp ?0.3 v ref ?0.1 v ref + 0.1 ? 0.6 n/a 36 n/a gtl ?0.3 v ref ?0.05 v ref +0.05 ? 0.4 n/a 32 n/a hstl i_12 ?0.3 v ref ?0.1 v ref +0.1 v cco + 0.3 25% v cco 75% v cco 6.3 6.3 hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 24 ?8 hstl iv (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 48 ?8 diff hstl i (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? diff hstl ii (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 i ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 i ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. for more information on pci33_3, pci66_3, and pci-x, refer to ug190 : virtex-5 fpga user guide, chapter 6, 3.3v i/o design guidelines . 6. supported drive strengths of 2, 4, 6, or 8 ma.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 8 ht dc specifications (ht_25) lvds dc specifications (lvds_25) extended lvds dc specif ications (lvdsext_25) ta bl e 8 : ht dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential output voltage r t = 100 across q and q signals 495 600 715 mv v od change in v od magnitude ?15 15 mv v ocm output common mode voltage r t = 100 across q and q signals 495 600 715 mv v ocm change in v ocm magnitude ?15 15 mv v id input differential voltage 200 600 1000 mv v id change in v id magnitude ?15 15 mv v icm input common mode voltage 440 600 780 mv v icm change in v icm magnitude ?15 15 mv ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.825 v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.125 1.250 1.375 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v ta bl e 1 0 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 across q and q signals ? 1.785 v v ol output low voltage for q and q r t = 100 across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q = high r t = 100 across q and q signals 350 ? 820 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.125 1.250 1.375 v v idiff differential input voltage (q ? q ), q = high (q ?q), q = high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differentia l input voltage = 350 mv 0.3 1.2 2.2 v
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 9 lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are co mpatible with devices toler ant of lower common-mode ranges. ta bl e 1 1 summarizes the dc output sp ecifications of lvpecl. for mo re information on using lvpecl , see ug190 : virtex-5 fpga user guide, chapter 6, selectio resources . powerpc 440 switchin g characteristics consult the embedded processor block in virtex-5 fpgas reference guide for further information. ta bl e 1 1 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 2.2 v v idiff differential input voltage (1,2) 0.100 1.5 v notes: 1. recommended input maximum voltage not to exceed v cco +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 2 : processor block switching characteristics clock name description speed grade units -3 -2 -1 cpmc440clk cpu clock 550 475 400 mhz cpminterconnectclk xbar clock 366.6 316.6 266.6 mhz cpmppcs0plbclk slave 0 plb clock (1) 183.3 158.3 133.3 mhz cpmppcs1plbclk slave 1 plb clock (1) 183.3 158.3 133.3 mhz cpmppcmplbclk master plb clock (1) 183.3 158.3 133.3 mhz cpmmcclk memory interface clock (1)(2) 366.6 316.6 266.6 mhz cpmfcmclk fcm clock (1) 275 237.5 200 mhz cpmdcrclk fpga logic dcr clock (1) 183.3 158.3 133.3 mhz cpmdma0llclk dma0 ll clock (1) 250 250 200 mhz cpmdma1llclk dma1 ll clock (1) 250 250 200 mhz cpmdma2llclk dma2 ll clock (1) 250 250 200 mhz cpmdma3llclk dma3 ll clock (1) 250 250 200 mhz jtgc440tck jtag clock 50 50 50 mhz cpmc440timerclock timer clock 275 237.5 200 mhz notes: 1. typical bus frequencies are provided for reference only, actual frequencies are user-design dependent. 2. refer to ds567 for maximum clock speed of designs using the ddr2 memory controller for powerpc? 440 processors.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 10 ta bl e 1 3 : processor block mib switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmmcclk 1.146 1.247 1.463 ps t ck_address cpmmcclk 1.017 1.136 1.38 ps t ck_data cpmmcclk 1.076 1.172 1.38 ps t control_ck cpmmcclk 0.736 0.844 0.941 ps t data_ck cpmmcclk 0.834 0.95 1.058 ps ta bl e 1 4 : processor block plbm sw itching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmppcmplbclk 0.971 1.095 1.354 ps t ck_address cpmppcmplbclk 1.215 1.372 1.673 ps t ck_data cpmppcmplbclk 1.115 1.257 1.535 ps t control_ck cpmppcmplbclk 1.7 1.79 1.86 ps t data_ck cpmppcmplbclk 0.774 0.914 1.059 ps ta bl e 1 5 : processor block plbs0 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmppcs0plbclk 1.063 1.196 1.462 ps t ck_data cpmppcs0plbclk 1.052 1.189 1.461 ps t control_ck cpmppcs0plbclk 1.307 1.545 1.836 ps t address_ck cpmppcs0plbclk 1.253 1.492 1.787 ps t data_ck cpmppcs0plbclk 0.825 0.971 1.124 ps ta bl e 1 6 : processor block plbs1 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmppcs1plbclk 1.083 1.234 1.525 ps t ck_data cpmppcs1plbclk 1.146 1.298 1.615 ps t control_ck cpmppcs1plbclk 1.335 1.596 1.921 ps t address_ck cpmppcs1plbclk 1.328 1.568 1.864 ps t data_ck cpmppcs1plbclk 0.821 0.969 1.127 ps
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 11 ta bl e 1 7 : processor block dma0 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmdma0llclk 1.256 1.42 1.665 ps t ck_data cpmdma0llclk 1.312 1.472 1.712 ps t control_ck cpmdma0llclk 0.453 0.558 0.716 ps t data_ck cpmdma0llclk ?0.105 ?0.105 ?0.104 ps ta bl e 1 8 : processor block dma1 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmdma1llclk 1.127 1.266 1.474 ps t ck_data cpmdma1llclk 1.266 1.418 1.645 ps t control_ck cpmdma1llclk 0.447 0.555 0.717 ps t data_ck cpmdma1llclk ?0.014 0.01 0.046 ps ta bl e 1 9 : processor block dma2 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmdma2llclk 1.101 1.235 1.437 ps t ck_data cpmdma2llclk 1.127 1.262 1.463 ps t control_ck cpmdma2llclk 0.771 0.924 1.155 ps t data_ck cpmdma2llclk 0.135 0.142 0.168 ps ta bl e 2 0 : processor block dma3 switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmdma3llclk 1.094 1.242 1.462 ps t ck_data cpmdma3llclk 1.056 1.184 1.376 ps t control_ck cpmdma3llclk 0.636 0.767 0.965 ps t data_ck cpmdma3llclk 0.087 0.119 0.116 ps
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 12 ta bl e 2 1 : processor block dcr switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmdcrclk t ck_address cpmdcrclk t ck_data cpmdcrclk t control_ck cpmdcrclk t address_ck cpmdcrclk t data_ck cpmdcrclk ta bl e 2 2 : processor block fcm switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control cpmfcmclk 0.967 1.084 1.324 ps t ck_data cpmfcmclk 1.041 1.158 1.4 ps t ck_instruction cpmfcmclk 0.701 0.818 1.06 ps t control_ck cpmfcmclk 1.057 1.218 1.395 ps t data_ck cpmfcmclk 0.608 0.698 0.768 ps t result_ck cpmfcmclk 0.608 0.698 0.768 ps ta bl e 2 3 : processor block misc switching characteristics clock name description reference clock speed grade units -3 -2 -1 clock-to-out and setup relative to clock t ck_control clk1 t ck_address clk2 t ck_data clk3 t control_ck clk4 t address_ck clk5 t data_ck clk6
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 13 gtp_dual tile specifications gtp_dual tile dc characteristics ta bl e 2 4 : absolute maximum ratings for gtp_dual tiles symbol description units mgtavccpll analog supply voltage for the gtp_du al shared pll relative to gnd ?0.5 to 1.32 v mgtavtttx analog supply voltage for the gtp_dual transmitters relative to gnd ?0.5 to 1.32 v mgtavttrx analog supply voltage for the gtp_dual receivers relative to gnd ?0.5 to 1.32 v mgtavcc analog supply voltage for the gtp_dual common circuits relative to gnd ?0.5 to 1.1 v mgtavttrxc analog supply voltage for the resi stor calibration circuit of the gtp_dual column ?0.5 to 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 2 5 : recommended operating conditions for gtp_dual tiles (1)(2) symbol description min max units mgtavccpll (1) analog supply voltage for the gtp_dual shared pll relative to gnd 1.14 1.26 v mgtavtttx (1) analog supply voltage for the gtp_dual transmitters relative to gnd 1.14 1.26 v mgtavttrx (1) analog supply voltage for the gtp_dual receivers relative to gnd 1.14 1.26 v mgtavcc (1) analog supply voltage for the gtp_dual common circuits relative to gnd 0.95 1.05 v mgtavttrxc (1) analog supply voltage for the resistor calibration circuit of the gtp_dual column 1.14 1.26 v notes: 1. each voltage listed requires the filter circuit described in ug196 : virtex-5 fpga rocketio gt p transceiver user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 2 6 : dc characteristics over recommended operating conditions for gtp_dual tiles (1) symbol description min typ max units i mgtavtttx gtp_dual tile transmitter termination supply current (2) 71 90 ma i mgtavccpll gtp_dual tile shared pll supply current 36 60 ma i mgtavttrxc gtp_dual tile resistor termination calibration supply current 0.1 0.5 ma i mgtavttrx gtp_dual tile receiver termination supply current (3) 0.1 0.5 ma i mgtavcc gtp_dual tile internal analog supply current 56 110 ma mgtr ref precision reference resistor for internal calibration termination 49.9 1% tolerance notes: 1. typical values are specified at nominal voltage, 25c, with a 3.2 gb/s line rate. 2. icc numbers are given per gtp_dual tile with both gtp transceivers operating with default settings. 3. ac coupled tx/rx link.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 14 gtp_dual tile dc input and output levels ta bl e 2 8 summarizes the dc output specifications of the gtp_dual tiles in virtex-5 fpgas. figure 1 shows the single- ended output voltage swing. figure 2 shows the peak-to-peak differential output voltage. consult ug196 : virtex-5 fpga rocketio gtp transceiver user guide for further details. ta bl e 2 7 : gtp_dual tile quiescent supply current symbol description typ (1) max units i avtttxq quiescent mgtavtttx (transmitter te rmination) supply current 8.5 18 ma i avccpllq quiescent mgtavccpll (pll) supply current 8 18 ma i avttrxq quiescent mgtavttrx (receiver termination) supply current. includes mgtavttrxcq. 0.1 0.8 ma i avccq quiescent mgtavcc (analog) supply current 2.5 11 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. device powered and unconfigured. 3. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 4. gtp_dual tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available gtp_dual tiles in the target lxt or sxt device. ta bl e 2 8 : gtp_dual tile dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled 3.2 gb/s 150 2000 mv external ac coupled > 3.2 gb/s 180 2000 mv v in absolute input voltage dc coupled ?400 mgtavttrx + 400 up to 1320 mv v cmin common mode input voltage dc coupled mgtavttrx = 1.2v 800 mv dv ppout differential peak-to-peak output voltage (1) txbufdiffctrl = 000 , tx_diff_boost = on 1400 mv v seout single-ended output voltage swing (1) txbufdiffctrl = 000 , tx_diff_boost = on 700 mv v cmout common mode output voltage equation based mgtavtttx = 1.2v 1200 ? amplitude/2 mv r in differential input resistance 90 100 120 r out differential output resistance 90 100 120 t oskew transmitter output skew 15 ps c ext recommended external ac coupling capacitor (2) 75 100 200 nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in ug196 : virtex-5 fpga rocketio gtp transceiver user guide and can result in values lower than reported in this table. 2. values outside of this range can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 1 figure 1: single-ended output voltage swing 0 +v p n v seout ds202_01_051607
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 15 ta bl e 2 9 summarizes the dc specifications of the clock input of the gtp_dual tile. figure 3 shows the single-ended input voltage swing. figure 4 shows the peak-to-peak differential clock input voltage swing. consult ug196 : virtex-5 fpga rocketio gtp transceiver user guide for further details. x-ref target - figure 2 figure 2: peak-to-peak differential output voltage ta bl e 2 9 : gtp_dual tile clock dc input specifications (1) symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 200 800 2000 mv v ise single-ended input voltage 100 400 1000 mv r in differential input resistance 80 105 130 c ext required external ac coupling capacitor 75 100 200 nf notes: 1. v min = 0v and v max = 1200mv x-ref target - figure 3 figure 3: single-ended clock input voltage swing peak-to-peak x-ref target - figure 4 figure 4: differential clock input voltage swing peak-to-peak 0 +v ?v p?n dv ppout d s 202_02_0 8 1 8 09 0 +v p n v ise ds202_03_052708 0 +v ?v p ? n v idiff ds202_04_052708
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 16 gtp_dual tile switching characteristics consult ug196 : virtex-5 fpga rocketio gtp transceiver user guide for further information. ta bl e 3 0 : gtp_dual tile performance symbol description speed grade units -3 -2 -1 f gtpmax maximum gtp transceiver data rate 3.75 3.75 3.2 gb/s f gpllmax maximum pll frequency 2.0 2.0 2.0 ghz f gpllmin minimum pll frequency 1.0 1.0 1.0 ghz ta bl e 3 1 : dynamic reconfiguration port (drp) in the gtp_dual tile switching characteristics symbol description speed grade units -3 -2 -1 f gtpdrpclk gtp dclk (drp clock) maximum frequency 200 175 150 mhz ta bl e 3 2 : gtp_dual tile reference cloc k switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range (1) clk 60 350 mhz t rclk reference clock rise time 20% ? 80% 200 400 ps t fclk reference clock fall time 80% ? 20% 200 400 ps t dcref reference clock duty cycle (2) clk 40 50 60 % t gjtt reference clock total jitter, peak-peak (3) clk 40 ps t lock clock recovery frequency acquisition time initial pll lock 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock 200 s notes: 1. the clock from the gtp_dual differential clock pin pair can be used for all serial bit rates. grefclk can be used for serial bit rates up to 1gb/s. 2. for reference clock rates above 325 mhz, a duty cycle of 45% to 55% must be maintained. 3. measured at the package pin. gtp_dual jitter characteristics measured using a clock with specification t gjtt . x-ref target - figure 5 figure 5: reference clock timing parameters ds202_05_100506 80% 20% t fclk t rclk
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 17 ta bl e 3 3 : gtp_dual tile user clock switching characteristics (1) symbol description conditions speed grade units -3 -2 -1 f txout txoutclk maximum frequency 375 375 320 mhz f rxrec rxrecclk maximum frequency 375 375 320 mhz t rx rxusrclk maximum frequency 375 375 320 mhz t rx2 rxusrclk2 maximum frequency rxdatawidth = 0 350 350 320 mhz rxdatawidth = 1 187.5 187.5 160 mhz t tx txusrclk maximum frequency 375 375 320 mhz t tx2 txusrclk2 maximum frequency txdatawidth = 0 350 350 320 mhz txdatawidth = 1 187.5 187.5 160 mhz notes: 1. clocking must be implemented as described in ug196 : virtex-5 fpga rocketio gtp transceiver user guide ta bl e 3 4 : gtp_dual tile transmitter switching characteristics symbol description min typ max units f gtptx serial data rate range 0.1 f gtpmax gb/s t rtx tx rise time 140 ps t ftx tx fall time 120 ps t llskew tx lane-to-lane skew (1) 855 ps v txoobvdpp electrical idle amplitude 20 mv t txoobtrans electrical idle transition time 40 ns t j3.75 total jitter (2) 3.75 gb/s 0.35 ui d j3.75 deterministic jitter (2) 0.19 ui t j3.2 total jitter (2) 3.20 gb/s 0.35 ui d j3.2 deterministic jitter (2) 0.19 ui t j2.5 total jitter (2) 2.50 gb/s 0.30 ui d j2.5 deterministic jitter (2) 0.14 ui t j2.0 total jitter (2) 2.00 gb/s 0.30 ui d j2.0 deterministic jitter (2) 0.14 ui t j1.25 total jitter (2) 1.25 gb/s 0.20 ui d j1.25 deterministic jitter (2) 0.10 ui t j1.00 total jitter (2) 1.00 gb/s 0.20 ui d j1.00 deterministic jitter (2) 0.10 ui t j500 total jitter (2) 500 mb/s 0.10 ui d j500 deterministic jitter (2) 0.04 ui t j100 total jitter (2) 100 mb/s 0.02 ui d j100 deterministic jitter (2) 0.01 ui notes: 1. using same refclk input with txenpmaphasealign enabled for up to four consecutive gtp_dual sites. 2. using pll_divsel_fb = 2, intdatawidth = 1. 3. all jitter values are based on a bit-error ratio of 1e ?12 .
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 18 ta bl e 3 5 : gtp_dual tile receiver switching characteristics symbol description min typ max units f gtprx serial data rate rx oversampler not enabled 0.5 f gtpmax gb/s rx oversampler enabled 0.1 0.5 gb/s r xoobvdpp oob detect threshold peak-to-peak oobdetect_threshold = 100 60 105 165 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 0 ppm r xrl run length (cid) internal ac capacitor bypassed 150 ui r xppmtol data/refclk ppm offset tolerance (2) cdr 2 nd -order loop disabled with pll_rxdivsel_out = 1 (3) ?200 200 ppm cdr 2 nd -order loop disabled with pll_rxdivsel_out = 2 (3) ?200 200 ppm cdr 2 nd -order loop disabled with pll_rxdivsel_out = 4 (3) ?100 100 ppm cdr 2 nd -order loop enabled ?1000 1000 ppm sj jitter tolerance (4) jt_sj 3.75 sinusoidal jitter (5) 3.75 gb/s 0.30 ui jt_sj 3.2 sinusoidal jitter (5) 3.20 gb/s 0.40 ui jt_sj 2.50 sinusoidal jitter (5) 2.50 gb/s 0.40 ui jt_sj 2.00 sinusoidal jitter (5) 2.00 gb/s 0.40 ui jt_sj 1.00 sinusoidal jitter (5) 1.00 gb/s 0.30 ui jt_sj 500 sinusoidal jitter (5) 500 mb/s 0.30 ui jt_sj 500 sinusoidal jitter (5) 500 mb/s os 0.30 ui jt_sj 100 sinusoidal jitter (5) 100 mb/s os 0.30 ui sj jitter tolerance with stressed eye (4) jt_tjse 3.2 total jitter wi th stressed eye (6) 3.20 gb/s 0.87 ui jt_sjse 3.2 sinusoidal jitter with stressed eye (6) 3.20 gb/s 0.30 ui notes: 1. using pll_rxdivsel_out = 1 only. 2. indicates the maximum offset between the receiver reference clock and the serial data. for example, a reference clock with 1 00 ppm resolution results in a maximum offset of 200 ppm between the reference clock and the serial data. 3. cdr 1st-order step size set to 2. 4. all jitter values are based on a bit error ratio of 1e ?12 . 5. using 80 mhz sinusoidal jitter only in the absence of deterministic and random jitter. 6. stimulus signal includes 0.4ui of dj and 0.17ui of rj. rx equalizer is enabled.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 19 gtx_dual tile specifications gtx_dual tile dc characteristics ta bl e 3 6 : absolute maximum ratings for gtx_dual tiles symbol description units mgtavccpll analog supply voltage for the gtx_du al shared pll relative to gnd ?0.5 to 1.1 v mgtavtttx analog supply voltage for the gtx_dual transmitters relative to gnd ?0.5 to 1.32 v mgtavttrx analog supply voltage for the gtx_dual receivers relative to gnd ?0.5 to 1.32 v mgtavcc analog supply voltage for the gtx_dual common circuits relative to gnd ?0.5 to 1.1 v mgtavttrxc analog supply voltage for the resi stor calibration circuit of the gtx_dual column ?0.5 to 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 3 7 : recommended operating conditions for gtx_dual tiles (1)(2) symbol description min max units mgtavccpll (1) analog supply voltage for the gtx_dual shared pll relative to gnd 0.95 1.05 v mgtavtttx (1) analog supply voltage for the gtx_dual transmitters relative to gnd 1.14 1.26 v mgtavttrx (1) analog supply voltage for the gtx_dual receivers relative to gnd 1.14 1.26 v mgtavcc (1) analog supply voltage for the gtx_dual common circuits relative to gnd 0.95 1.05 v mgtavttrxc (1) analog supply voltage for the resistor calibration circuit of the gtx_dual column 1.14 1.26 v notes: 1. each voltage listed requires the filter circuit described in ug198 : virtex-5 fpga rocketio gt x transceiver user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 3 8 : dc characteristics over recommended operating conditions for gtx_dual tiles (1) symbol description min typ max units i mgtavtttx gtx_dual tile transmitter termination supply current (2) 43.3 86.3 ma i mgtavccpll gtx_dual tile shared pll supply current 38.0 99.4 ma i mgtavttrxc gtx_dual tile resistor termination calibration supply current 0.1 0.5 ma i mgtavttrx gtx_dual tile receiver termination supply current (3) 40.3 56.5 ma i mgtavcc gtx_dual tile internal analog supply current 80.5 179.5 ma mgtr ref precision reference resistor for internal calibration termination 59.0 1% tolerance notes: 1. typical values are specified at nominal voltage, 25c, with a 3.2 gb/s line rate. 2. i cc numbers are given per gtx_dual tile with both gtx transceivers operating with default settings. 3. ac coupled tx/rx link. 4. values for currents other than the values specified in this table can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 20 gtx_dual tile dc input and output levels ta bl e 4 0 summarizes the dc output specifications of the gtx_dual tiles in virtex-5 fpgas. figure 6 shows the single- ended output voltage swing. figure 7 shows the peak-to-peak differential output voltage. consult ug198 : virtex-5 fpga rocketio gtx transceiver user guide for further details. ta bl e 3 9 : gtx_dual tile quiescent supply current symbol description typ (1) max units i avtttxq quiescent mgtavtttx (transmitter termination) supply current 8.2 21.6 ma i avccpllq quiescent mgtavccpll (p ll) supply current 0.8 4.8 ma i avttrxq quiescent mgtavttrx (receiver termination) supply current. includes mgtavttrxcq. 1.2 12.0 ma i avccq quiescent mgtavcc (analog) supply current 9.0 50.4 ma notes: 1. typical values are specified at nominal voltage, 25c. 2. device powered and unconfigured. 3. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 4. gtx_dual tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available gtx_dual tiles in the target txt or fxt device. ta bl e 4 0 : gtx_dual tile dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled 4.25 gb/s 125 1800 mv external ac coupled > 4.25 gb/s 125 1800 mv v in absolute input voltage dc coupled mgtavttrx = 1.2v ?400 mgtavttrx +400 up to 1320 mv v cmin common mode input voltage dc coupled mgtavttrx = 1.2v 800 mv dv ppout differential peak-to-peak output voltage (1) txbufdiffctrl = 111 1400 mv v seout single-ended output voltage swing (1) txbufdiffctrl = 111 700 mv v cmout common mode output voltage equation based mgtavtttx = 1.2v 1200?dv ppout /2 mv r in differential input resistance 85 100 120 r out differential output resistance 85 100 120 t oskew transmitter output skew 2 8 ps c ext recommended external ac coupling capacitor (2) 75 100 200 nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in ug198 : virtex-5 fpga rocketio gtx transceiver user guide and can result in values lower than reported in this table. 2. values outside of this range can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 6 figure 6: single-ended output voltage swing 0 +v p n v seout ds202_01_051607
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 21 ta bl e 4 1 summarizes the dc specifications of the clock input of the gtx_dual tile. figure 8 shows the single-ended input voltage swing. figure 9 shows the peak-to-peak differential clock input voltage swing. consult ug198 : virtex-5 fpga rocketio gtx transceiver user guide for further details. x-ref target - figure 7 figure 7: peak-to-peak differential output voltage ta bl e 4 1 : gtx_dual tile clock dc input level specification (1) symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 210 800 2000 mv v ise single-ended input voltage 105 400 1000 mv r in differential input resistance 90 105 130 c ext required external ac coupling capacitor 100 nf notes: 1. v min = 0v and v max = 1200mv x-ref target - figure 8 figure 8: single-ended clock input voltage swing peak-to-peak x-ref target - figure 9 figure 9: differential clock input voltage swing peak-to-peak 0 +v ?v p?n dv ppout d s 202_02_0 8 1 8 09 0 +v p n v ise ds202_03_052708 0 +v ?v p ? n v idiff ds202_04_052708
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 22 gtx_dual tile switching characteristics consult ug198 : virtex-5 fpga rocketio gtx transceiver user guide for further information. ta bl e 4 2 : gtx_dual tile performance symbol description speed grade units -3 -2 -1 f gtxmax maximum gtx transceiver data rate 6.5 6.5 4.25 gb/s f gpllmax maximum pll frequency 3.25 3.25 3.25 ghz f gpllmin minimum pll frequency 1.48 1.48 1.48 ghz ta bl e 4 3 : dynamic reconfiguration port (drp) in the gtx_dual tile switching characteristics symbol description speed grade units -3 -2 -1 f gtxdrpclk gtx dclk (drp clock) maximum frequency 200 175 150 mhz ta bl e 4 4 : gtx_dual tile reference cloc k switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range (1) clk 60 650 mhz t rclk reference clock rise time 20% ? 80% 200 ps t fclk reference clock fall time 80% ? 20% 200 ps t dcref reference clock duty cycle clk 40 50 60 % t gjtt reference clock total jitter (2, 3) at 100 khz ?145 dbc/hz at 1 mhz ?150 dbc/hz t lock clock recovery frequency acquisition time initial pll lock 0.25 1 ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock 200 s notes: 1. grefclk can be used for serial bit rates up to 1 gb/s; however, jitter specifications are not guaranteed when using grefclk. 2. gtx_dual jitter characteristics measured using a clock with specification t gjtt . a reference clock with higher phase noise can be used with link margin trade off. 3. the selection of the reference clock is application dependent. this parameter describes the quality of the reference clock us ed during transceiver jitter characterization - see ta bl e 4 6 and ta b l e 4 7 . x-ref target - figure 10 figure 10: reference clock timing parameters ds202_05_100506 80% 20% t fclk t rclk
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 23 ta bl e 4 5 : gtx_dual tile user clock switching characteristics (1) symbol description conditions device speed grade units -3 -2 -1 f txout txoutclk maximum frequency internal 20-bit datapath fxt 325 325 212.5 mhz txt - 325 212.5 mhz internal 16-bit datapa th fxt 406.25 406.25 265.625 mhz txt - 406.25 265.625 mhz f rxrec rxrecclk maximum frequency fxt 406.25 406.25 265.625 mhz txt - 406.25 265.625 mhz t rx rxusrclk maximum frequency fxt 406.25 406.25 265.625 mhz txt - 406.25 265.625 mhz t rx2 rxusrclk2 maximum frequency 1 byte interface fxt 375 312.5 235.625 mhz 2 byte interface 406.25 390.625 265.625 mhz 4 byte interface 203.125 203.125 132.813 mhz 1 byte interface txt - 312.5 235.625 mhz 2 byte interface - 265.625 265.625 mhz 4 byte interface - 203.125 132.813 mhz t tx txusrclk maximum frequen cy fxt 406.25 406.25 265.625 mhz txt - 406.25 265.625 mhz t tx2 txusrclk2 maximum frequency 1 byte interface fxt 375 312.5 235.625 mhz 2 byte interface 406.25 390.625 265.625 mhz 4 byte interface 203.125 203.125 132.813 mhz 1 byte interface txt - 312.5 235.625 mhz 2 byte interface - 265.625 265.625 mhz 4 byte interface - 203.125 132.813 mhz notes: 1. clocking must be implemented as described in ug198 : virtex-5 fpga rocketio gtx transceiver user guide . ta bl e 4 6 : gtx_dual tile transmitter switching characteristics symbol description condition min typ max units f gtxtx serial data rate range 0.15 f gtxmax gb/s t rtx tx rise time 20%?80% 120 ps t ftx tx fall time 80%?20% 120 ps t llskew tx lane-to-lane skew (1) 350 ps v txoobvdpp electrical idle amplitude 15 mv t txoobtransition electrical idle transition time 75 ns t j6.5 total jitter (2) 6.5 gb/s 0.33 ui d j6.5 deterministic jitter (2) 0.17 ui t j5.0 total jitter (2) 5.0 gb/s 0.33 ui d j5.0 deterministic jitter (2) 0.15 ui t j4.25 total jitter (2) 4.25 gb/s 0.33 ui d j4.25 deterministic jitter (2) 0.14 ui
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 24 t j3.75 total jitter (2) 3.75 gb/s 0.34 ui d j3.75 deterministic jitter (2) 0.16 ui t j3.2 total jitter (2) 3.2 gb/s 0.20 ui d j3.2 deterministic jitter (2) 0.10 ui t j3.2l total jitter (2) 3.2 gb/s (3) 0.36 ui d j3.2l deterministic jitter (2) 0.16 ui t j2.5 total jitter (2) 2.5 gb/s 0.20 ui d j2.5 deterministic jitter (2) 0.08 ui t j1.25 total jitter (2) 1.25 gb/s 0.15 ui d j1.25 deterministic jitter (2) 0.06 ui t j750 total jitter (2)(4) 750 mb/s 0.10 ui d j750 deterministic jitter (2)(4) 0.03 ui t j150 total jitter (2)(4) 150 mb/s 0.02 ui d j150 deterministic jitter (2)(4) 0.01 ui notes: 1. using same refclk input with txenpmaphasealign enab led for up to four consecutive gtx_dual sites. 2. using pll_divsel_fb = 2, intdatawidth = 1. these values are no t intended for protocol specif ic compliance determinations. 3. pll frequency at 1.6 ghz and outdiv = 1. 4. grefclk can be used for serial data rates up to 1.0 gb/s, but performance is not guaranteed. ta bl e 4 7 : gtx_dual tile receiver switching characteristics symbol description min typ max units f gtxrx serial data rate rx oversampler not enabled 0.75 f gtxmax gb/s rx oversampler enabled 0.15 0.75 gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data oobdetect_threshold = 110 75 ns r xoobvdpp oob detect threshold peak-to-peak oobdetect_threshold = 110 55 135 mv r xsst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 0 ppm r xrl run length (cid) internal ac capacitor bypassed 512 ui r xppmtol data/refclk ppm offset tolerance (2) cdr 2 nd -order loop disabled ?200 200 ppm cdr 2 nd -order loop enabled ?2000 2000 ppm sj jitter tolerance (3) jt_sj 6.5 sinusoidal jitter (4) 6.5 gb/s 0.44 ui jt_sj 5.0 sinusoidal jitter (4) 5.0 gb/s 0.44 ui jt_sj 4.25 sinusoidal jitter (4) 4.25 gb/s 0.44 ui jt_sj 3.75 sinusoidal jitter (4) 3.75 gb/s 0.44 ui jt_sj 3.2 sinusoidal jitter (4) 3.2 gb/s 0.45 ui jt_sj 3.2l sinusoidal jitter (4) 3.2 gb/s (5) 0.45 ui jt_sj 2.5 sinusoidal jitter (4) 2.5 gb/s 0.50 ui jt_sj 1.25 sinusoidal jitter (4) 1.25 gb/s 0.50 ui ta bl e 4 6 : gtx_dual tile transmitter switching characteristics (cont?d) symbol description condition min typ max units
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 25 crc block switching characteristics ethernet mac switching characteristics consult ug194 : virtex-5 fpga tri-mode ethernet media access controller user guide for further information. endpoint block for pci express de signs switching characteristics consult ug197 : virtex-5 fpga integrated endpoint block for pci express designs user guide for further information. jt_sj 750 sinusoidal jitter (4)(6) 750 mb/s 0.57 ui jt_sj 150 sinusoidal jitter (4)(6) 150 mb/s 0.57 ui sj jitter tolerance with stressed eye (3) jt_tjse 4.25 total jitter wi th stressed eye (7) 4.25 gb/s 0.69 ui jt_sjse 4.25 sinusoidal jitter with stressed eye (7) 4.25 gb/s 0.1 ui notes: 1. using pll_rxdivsel_out = 1, 2, and 4. 2. indicates the maximum offset between the receiver reference clock and the serial data. for example, a reference clock with 1 00 ppm resolution results in a maximum offset of 200 ppm between the reference clock and the serial data. 3. all jitter values are based on a bit error ratio of 1e ?12 . 4. using 80 mhz sinusoidal jitter only in the absence of deterministic and random jitter. 5. pll frequency at 1.6 ghz and outdiv = 1. 6. grefclk can be used for serial data rates up to 1.0 gb/s, but performance is not guaranteed. 7. composite jitter with rx equalizer enabled. dfe disabled. ta bl e 4 8 : crc block switching characteristics symbol description speed grade units -3 -2 -1 f crc crcclk maximum frequency 325 325 270 mhz ta bl e 4 9 : maximum ethernet mac performance symbol description conditions speed grade units -3 -2 -1 f temacclient client interface maximum frequency 10 mb/s ? 8-bit width 1.25 1.25 1.25 mhz 100 mb/s ? 8-bit width 12.5 12.5 12.5 mhz 1000 mb/s ? 8-bit width 125 125 125 mhz 2000 mb/s ? 16-bit width 125 125 125 mhz f temacphy physical interface maximum frequency 10 mb/s ? 4-bit width 2.5 2.5 2.5 mhz 100 mb/s ? 4-bit width 25 25 25 mhz 1000 mb/s ? 8-bit width 125 125 125 mhz 2000 mb/s ? 8-bit width 250 250 250 mhz ta bl e 5 0 : maximum performance for pci express designs symbol description speed grade units -3 -2 -1 f pciecore core clock maximum frequency 250 250 250 mhz f pcieuser user clock maximum frequency 250 250 250 mhz ta bl e 4 7 : gtx_dual tile receiver switching characteristics (cont?d) symbol description min typ max units
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 26 system monitor analog-to-digit al converter specification ta bl e 5 1 : analog-to-digital specifications parameter symbol comments/conditions min typ max units av dd =2.5v2%, v refp = 2.5v, v refn = 0v, adcclk = 5.2 mhz, t a =t min to t max , typical values at t a =+25c dc accuracy: all external input channels such as v p /v n and v auxp [15:0]/v auxn [15:0], unipolar mode, and common mode = 0v resolution 10 bits integral nonlinearity inl 2 lsbs differential nonlinearity dnl no missing codes (t min to t max ) guaranteed monotonic 0.9 lsbs unipolar offset error (1) uncalibrated 2 30 lsbs bipolar offset error (1) uncalibrated measured in bipolar mode 2 30 lsbs gain error (1) uncalibrated 0.2 2 % bipolar gain error (1) uncalibrated measured in bipolar mode 0.2 2 % total unadjusted error (uncalibrated) tue deviation from ideal transfer function. v refp ?v refn = 2.5v 10 lsbs total unadjusted error (calibrated) tue deviation from ideal transfer function. v refp ?v refn = 2.5v 1 2 lsbs calibrated gain temperature coefficient variation of fs code with temperature 0.01 lsb/c dc common-mode reject cmrr dc v n = v cm = 0.5v 0.5v, v p ?v n = 100mv 70 db conversion rate (2) conversion time - continuous t conv number of clk cycles 26 32 conversion time - event t conv number of clk cycles 21 t/h acquisition time t acq number of clk cycles 4 drp clock frequency dclk drp clock frequency 8 250 mhz adc clock frequency adcclk derived from dclk 1 5.2 mhz clk duty cycle 40 60 % analog inputs (3) dedicated analog inputs input voltage range v p - v n unipolar operation 0 1 volts differential inputs ?0.25 +0.25 unipolar common mode range (fs input) 0 +0.5 differential common mode range (fs input) +0.3 +0.7 bandwidth 20 mhz auxiliary analog inputs input voltage range v auxp[0] /v auxn[0] to v auxp[15] /v auxn[15] unipolar operation 0 1 volts differential operation ?0.25 +0.25 unipolar common mode range (fs input) 0 +0.5 differential common mode range (fs input) +0.3 +0.7 bandwidth 10 khz input leakage current a/d not converting, adcclk stopped 1.0 a input capacitance 10 pf on-chip supply monitor error v ccint and v ccaux with calibration enabled 1.0 % reading on-chip temperature monitor error ?40c to +125c with calibration enabled 4 c
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 27 external reference inputs (4) positive reference input voltage range v refp measured relative to v refn 2.45 2.5 2.55 volts negative reference input voltage range v refn measured relative to agnd ?50 0 100 mv input current i ref adcclk = 5.2 mhz 100 a power requirements analog power supply av dd measured relative to av ss 2.45 2.5 2.55 volts analog supply current ai dd adcclk = 5.2 mhz 5 13 ma notes: 1. offset and gain errors are removed by enabling the system monitor automatic gain calibration feature. see ug192 : virtex-5 fpga system monitor user guide . 2. see "system monitor timing" in ug192 : virtex-5 fpga system monitor user guide . 3. see "analog inputs" in ug192 : virtex-5 fpga system monitor user guide for a detailed description. 4. any variation in the reference voltage from the nominal v refp = 2.5v and v refn = 0v will result is a deviation from the ideal transfer function.this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted. ta bl e 5 1 : analog-to-digital specifications (cont?d) parameter symbol comments/conditions min typ max units
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 28 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-5 devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics, page 30 . ta b l e 5 2 shows internal (reg ister-to-register) performance. ta bl e 5 2 : register-to-register performance description register-to-register (with i/o delays) units speed grade -3 -2 -1 basic functions 16:1 multiplexer 550 500 450 mhz 32:1 multiplexer 550 500 450 mhz 64:1 multiplexer 511 467 407 mhz 9 x 9 logic multiplier with 4 pipe stages 468 438 428 mhz 9 x 9 logic multiplier with 5 pipe stages 550 500 428 mhz 16-bit adder 550 500 450 mhz 32-bit adder 550 500 447 mhz 64-bit adder 423 377 323 mhz register to lut to register 550 500 450 mhz 16-bit counter 550 500 450 mhz 32-bit counter 550 500 450 mhz 64-bit counter 428 381 333 mhz memory cascaded block ram (64k) 500 450 400 mhz block ram pipelined single-port 512 x 36 bits 550 500 450 mhz single-port 4096 x 4 bits 550 500 450 mhz dual-port a: 4096 x 4 bits and b: 1024 x 18 bits 550 500 450 mhz distributed ram single-port 16 x 8 550 500 450 mhz single-port 32 x 8 550 500 450 mhz single-port 64 x 8 550 500 450 mhz dual-port 16 x 8 mhz shift register chain 16-bit 550 500 450 mhz 32-bit 550 500 450 mhz 64-bit 550 500 438 mhz
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 29 dedicated arithmetic logic dsp48e quad 12-bit adder/subtracter 550 500 450 mhz dsp48e dual 24-bit adder/subtracter 550 500 450 mhz dsp48e 48-bit adder/subtracter 550 500 450 mhz dsp48e 48-bit counter 550 500 450 mhz dsp48e 48-bit comparator 550 500 450 mhz dsp48e 25 x 18 bit pipelined multiplier 550 500 450 mhz dsp48e direct 4-tap fir filter pipelined 510 458 397 mhz dsp48e systolic n-tap fir filter pipelined 550 500 450 mhz notes: 1. device used is the xc5vlx50t- ff1136 ta bl e 5 3 : interface performances description speed grade -3 -2 -1 networking applications sfi-4.1 (sdr lvds interface) (1) 710 mhz 710 mhz 645 mhz spi-4.2 (ddr lvds interface) (2) 1.25 gb/s 1.25 gb/s 1.0 gb/s memory interfaces ddr (3) 200 mhz 200 mhz 200 mhz ddr2 (4) 333 mhz 300 mhz 267 mhz qdr ii sram (5) 300 mhz 300 mhz 250 mhz rldram ii (6) 333 mhz 300 mhz 250 mhz notes: 1. performance defined using design implementation described in ap plication note xapp856: sfi-4.1 16-channel sdr interface with bus alignment 2. performance defined using design implementation described in application note xapp860: 16-channel, ddr lvds interface with re al-time window monitoring 3. performance defined using design implementation described in application note xapp851: ddr sdram controller 4. performance defined usin g design implementation described in application note xa pp858: high-performance ddr2 sdram interface data capture 5. performance defined using design implementation described in application note xapp853: qdrii sram interface 6. performance defined using design implementation described in application note xapp852: synthesizable rldram ii controller ta bl e 5 2 : register-to-register performance (cont?d) description register-to-register (with i/o delays) units speed grade -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 30 switching characteristics all values represented in this data sheet are based on speed specification version 1.62. switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta bl e 5 4 correlates the current status of each virtex-5 device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-5 devices. ta b l e 5 4 : virtex-5 device speed grade designations device speed grade designations advance preliminary production xc5vlx20t -2, -1 xc5vlx30 -3, -2, -1 xc5vlx30t -3, -2, -1 xc5vlx50 -3, -2, -1 xc5vlx50t -3, -2, -1 xc5vlx85 -3, -2, -1 xc5vlx85t -3, -2, -1 XC5VLX110 -3, -2, -1 XC5VLX110t -3, -2, -1 xc5vlx155 -3, -2, -1 xc5vlx155t -3, -2, -1 xc5vlx220 -2, -1 xc5vlx220t -2, -1 xc5vlx330 -2, -1 xc5vlx330t -2, -1 xc5vsx35t -3, -2, -1 xc5vsx50t -3, -2, -1 xc5vsx95t -2, -1 xc5vsx240t -2, -1 xc5vtx150t -2, -1 xc5vtx240t -2, -1 xc5vfx30t -3, -2, -1 xc5vfx70t -3, -2, -1 xc5vfx100t -3, -2, -1 xc5vfx130t -3, -2, -1 xc5vfx200t -2, -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 31 production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 5 5 lists the production released virtex-5 family member, speed grade, and the minimum corresponding supported speed specification version and ise? software revisions. the ise software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. ta b l e 5 5 : virtex-5 device production software and speed specification release device speed grade designations -3 -2 -1 xc5vlx20t n/a ise 10.1 sp2 v1.61 xc5vlx30 ise 9.2i sp4 v1.58 xc5vlx30t ise 9.2i sp4 v1.58 xc5vlx50 ise 9.2i sp4 v1.58 xc5vlx50t ise 9.2i sp4 v1.58 xc5vlx85 ise 9.2i sp4 v1.58 xc5vlx85t ise 9.2i sp4 v1.58 XC5VLX110 ise 9.2i sp4 v1.58 XC5VLX110t ise 9.2i sp4 v1.58 xc5vlx155 ise 10.1 sp2 v1.61 xc5vlx155t ise 10.1 sp2 v1.61 xc5vlx220 n/a ise 9.2i sp4 v1.58 xc5vlx220t n/a ise 9.2i sp4 v1.58 xc5vlx330 n/a ise 9.2i sp4 v1.58 xc5vlx330t n/a ise 9.2i sp4 v1.58 xc5vsx35t ise 9.2i sp4 v1.58 xc5vsx50t ise 9.2i sp4 v1.58 xc5vsx95t n/a ise 9.2i sp4 v1.58 xc5vsx240t n/a ise 10.1 sp3 v1.63 xc5vtx150t n/a ise 10.1 sp3 v1.63 xc5vtx240t n/a ise 10.1 sp3 v1.63 xc5vfx30t ise 10.1 sp3 v1.63 xc5vfx70t ise 10.1 sp3 v1.63 xc5vfx100t ise 10.1 sp3 v1.63 xc5vfx130t ise 10.1 sp3 v1.63 xc5vfx200t n/a ise 10.1 sp3 v1.63 notes: 1. blank entries indicate a device and/or speed grade in advance or preliminary status.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 32 iob pad input/output/3-state switching characteristics ta bl e 5 6 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of th e selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. ta b l e 5 7 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 5 6 : iob switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -3 -2 -1 -3 -2 -1 lvds_25 0.80 0.90 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns lvdsext_25 1.01 1.16 1.30 1.1 7 1.34 1.49 1.17 1.34 1.49 ns ht_25 0.80 0.90 1.06 1.10 1. 26 1.40 1.10 1.26 1.40 ns blvds_25 0.80 0.90 1.06 1.24 1.38 1.58 1.24 1.38 1.58 ns rsds_25 (point to point) 0.80 0.9 0 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns ulvds_25 0.80 0.90 1.06 1.10 1.27 1.41 1.10 1.27 1.41 ns pci33_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns pci66_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns pci-x 0.62 0.70 0.82 1.40 1.56 1.80 1.40 1.56 1.80 ns gtl 0.76 0.85 1.00 1.47 1.63 1.86 1.47 1.63 1.86 ns gtlp 0.76 0.85 1.00 1.51 1. 68 1.93 1.51 1.68 1.93 ns hstl_i 0.76 0.85 1.00 1.42 1.57 1.79 1.42 1.57 1.79 ns hstl_ii 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns hstl_iii 0.76 0.85 1.00 1.44 1.60 1.85 1.44 1.60 1.85 ns hstl_iv 0.76 0.85 1.00 1.44 1.60 1.83 1.44 1.60 1.83 ns hstl_i _18 0.76 0.85 1.00 1. 40 1.55 1.77 1.40 1.55 1.77 ns hstl_ii _18 0.76 0.85 1.00 1.36 1.51 1.72 1.36 1.51 1.72 ns hstl_iii _18 0.76 0.85 1.00 1. 45 1.61 1.85 1.45 1.61 1.85 ns hstl_iv_18 0.76 0.85 1.00 1. 41 1.57 1.81 1.41 1.57 1.81 ns sstl2_i 0.76 0.85 1.00 1.48 1.64 1.87 1.48 1.64 1.87 ns sstl2_ii 0.76 0.85 1.00 1.40 1.55 1.76 1.40 1.55 1.76 ns lvttl, slow, 2 ma 0.62 0.70 0.82 4.10 4.47 5.01 4.10 4.47 5.01 ns lvttl, slow, 4 ma 0.62 0.70 0.82 2.87 3.09 3.41 2.87 3.09 3.41 ns lvttl, slow, 6 ma 0.62 0.70 0.82 2.66 2.91 3.29 2.66 2.91 3.29 ns lvttl, slow, 8 ma 0.62 0.70 0.82 2.09 2.30 2.61 2.09 2.30 2.61 ns lvttl, slow, 12 ma 0.62 0.70 0. 82 1.94 2.15 2.46 1.94 2.15 2.46 ns lvttl, slow, 16 ma 0.62 0.70 0. 82 1.84 2.04 2.34 1.84 2.04 2.34 ns lvttl, slow, 24 ma 0.62 0.70 0. 82 1.87 2.07 2.38 1.87 2.07 2.38 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 33 lvttl, fast, 2 ma 0.62 0.70 0.82 3.32 3.61 4.05 3.32 3.61 4.05 ns lvttl, fast, 4 ma 0.62 0.70 0.82 2.32 2.55 2.90 2.32 2.55 2.90 ns lvttl, fast, 6 ma 0.62 0.70 0.82 2.10 2.31 2.63 2.10 2.31 2.63 ns lvttl, fast, 8 ma 0.62 0.70 0.82 1.65 1.82 2.09 1.65 1.82 2.09 ns lvttl, fast, 12 ma 0.62 0.70 0. 82 1.47 1.63 1.89 1.47 1.63 1.89 ns lvttl, fast, 16 ma 0.62 0.70 0. 82 1.41 1.57 1.81 1.41 1.57 1.81 ns lvttl, fast, 24 ma 0.62 0.70 0. 82 1.36 1.52 1.74 1.36 1.52 1.74 ns lvcmos33, slow, 2 ma 0.62 0.70 0.8 2 3.63 3.96 4.44 3.63 3.96 4.44 ns lvcmos33, slow, 4 ma 0.62 0.70 0.8 2 2.82 3.09 3.49 2.82 3.09 3.49 ns lvcmos33, slow, 6 ma 0.62 0.70 0.8 2 2.61 2.86 3.24 2.61 2.86 3.24 ns lvcmos33, slow, 8 ma 0.62 0.70 0.8 2 2.06 2.26 2.57 2.06 2.26 2.57 ns lvcmos33, slow, 12 ma 0.62 0.70 0. 82 1.95 2.14 2.42 1.95 2.14 2.42 ns lvcmos33, slow, 16 ma 0.62 0.70 0. 82 1.86 2.04 2.31 1.86 2.04 2.31 ns lvcmos33, slow, 24 ma 0.62 0.70 0. 82 1.87 2.07 2.35 1.87 2.07 2.35 ns lvcmos33, fast, 2 ma 0.62 0.70 0.82 2.94 3.20 3.59 2.94 3.20 3.59 ns lvcmos33, fast, 4 ma 0.62 0.70 0.82 2.27 2.50 2.84 2.27 2.50 2.84 ns lvcmos33, fast, 6 ma 0.62 0.70 0.82 2.06 2.27 2.59 2.06 2.27 2.59 ns lvcmos33, fast, 8 ma 0.62 0.70 0.82 1.61 1.79 2.05 1.61 1.79 2.05 ns lvcmos33, fast, 12 ma 0.62 0.70 0. 82 1.45 1.61 1.86 1.45 1.61 1.86 ns lvcmos33, fast, 16 ma 0.62 0.70 0. 82 1.40 1.56 1.80 1.40 1.56 1.80 ns lvcmos33, fast, 24 ma 0.62 0.70 0. 82 1.35 1.51 1.74 1.35 1.51 1.74 ns lvcmos25, slow, 2 ma 0.61 0.70 0.8 2 3.67 3.97 4.42 3.67 3.97 4.42 ns lvcmos25, slow, 4 ma 0.61 0.70 0.8 2 2.37 2.60 2.94 2.37 2.60 2.94 ns lvcmos25, slow, 6 ma 0.61 0.70 0.8 2 2.19 2.41 2.74 2.19 2.41 2.74 ns lvcmos25, slow, 8 ma 0.61 0.70 0.8 2 2.05 2.26 2.56 2.05 2.26 2.56 ns lvcmos25, slow, 12 ma 0.61 0.70 0. 82 2.10 2.31 2.63 2.10 2.31 2.63 ns lvcmos25, slow, 16 ma 0.61 0.70 0. 82 1.84 2.02 2.30 1.84 2.02 2.30 ns lvcmos25, slow, 24 ma 0.61 0.70 0. 82 1.83 2.04 2.34 1.83 2.04 2.34 ns lvcmos25, fast, 2 ma 0.61 0.70 0.82 3.14 3.41 3.82 3.14 3.41 3.82 ns lvcmos25, fast, 4 ma 0.61 0.70 0.82 1.89 2.08 2.37 1.89 2.08 2.37 ns lvcmos25, fast, 6 ma 0.61 0.70 0.82 1.74 1.92 2.20 1.74 1.92 2.20 ns lvcmos25, fast, 8 ma 0.61 0.70 0.82 1.66 1.83 2.09 1.66 1.83 2.09 ns lvcmos25, fast, 12 ma 0.61 0.70 0. 82 1.52 1.69 1.94 1.52 1.69 1.94 ns lvcmos25, fast, 16 ma 0.61 0.70 0. 82 1.43 1.60 1.85 1.43 1.60 1.85 ns lvcmos25, fast, 24 ma 0.61 0.70 0. 82 1.40 1.54 1.76 1.40 1.54 1.76 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -3 -2 -1 -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 34 lvcmos18, slow, 2 ma 0.67 0.76 0.8 9 4.20 4.56 5.09 4.20 4.56 5.09 ns lvcmos18, slow, 4 ma 0.67 0.76 0.8 9 3.03 3.32 3.75 3.03 3.32 3.75 ns lvcmos18, slow, 6 ma 0.67 0.76 0.8 9 2.37 2.61 2.97 2.37 2.61 2.97 ns lvcmos18, slow, 8 ma 0.67 0.76 0.8 9 2.15 2.37 2.69 2.15 2.37 2.69 ns lvcmos18, slow, 12 ma 0.67 0.76 0. 89 1.95 2.16 2.47 1.95 2.16 2.47 ns lvcmos18, slow, 16 ma 0.67 0.76 0. 89 1.93 2.14 2.45 1.93 2.14 2.45 ns lvcmos18, fast, 2 ma 0.67 0.76 0.89 3.41 3.71 4.16 3.41 3.71 4.16 ns lvcmos18, fast, 4 ma 0.67 0.76 0.89 2.36 2.61 2.98 2.36 2.61 2.98 ns lvcmos18, fast, 6 ma 0.67 0.76 0.89 1.87 2.06 2.35 1.87 2.06 2.35 ns lvcmos18, fast, 8 ma 0.67 0.76 0.89 1.69 1.87 2.13 1.69 1.87 2.13 ns lvcmos18, fast, 12 ma 0.67 0.76 0. 89 1.51 1.68 1.93 1.51 1.68 1.93 ns lvcmos18, fast, 16 ma 0.67 0.76 0. 89 1.44 1.61 1.86 1.44 1.61 1.86 ns lvcmos15, slow, 2 ma 0.73 0.83 0.9 8 3.50 3.84 4.34 3.50 3.84 4.34 ns lvcmos15, slow, 4 ma 0.73 0.83 0.9 8 2.17 2.40 2.74 2.17 2.40 2.74 ns lvcmos15, slow, 6 ma 0.73 0.83 0.9 8 1.99 2.20 2.52 1.99 2.20 2.52 ns lvcmos15, slow, 8 ma 0.73 0.83 0.9 8 1.91 2.12 2.43 1.91 2.12 2.43 ns lvcmos15, slow, 12 ma 0.73 0.83 0. 98 1.74 1.95 2.25 1.74 1.95 2.25 ns lvcmos15, slow, 16 ma 0.73 0.83 0. 98 1.71 1.91 2.20 1.71 1.91 2.20 ns lvcmos15, fast, 2 ma 0.73 0.83 0.98 2.80 3.07 3.48 2.80 3.07 3.48 ns lvcmos15, fast, 4 ma 0.73 0.83 0.98 1.76 1.95 2.23 1.76 1.95 2.23 ns lvcmos15, fast, 6 ma 0.73 0.83 0.98 1.62 1.80 2.06 1.62 1.80 2.06 ns lvcmos15, fast, 8 ma 0.73 0.83 0.98 1.57 1.74 2.00 1.57 1.74 2.00 ns lvcmos15, fast, 12 ma 0.73 0.83 0. 98 1.43 1.60 1.86 1.43 1.60 1.86 ns lvcmos15, fast, 16 ma 0.73 0.83 0. 98 1.37 1.53 1.77 1.37 1.53 1.77 ns lvcmos12, slow, 2 ma 0.84 0.96 1.1 4 3.58 3.98 4.58 3.58 3.98 4.58 ns lvcmos12, slow, 4 ma 0.84 0.96 1.1 4 2.10 2.33 2.66 2.10 2.33 2.66 ns lvcmos12, slow, 6 ma 0.84 0.96 1.1 4 2.00 2.18 2.45 2.00 2.18 2.45 ns lvcmos12, slow, 8 ma 0.84 0.96 1.1 4 1.91 2.14 2.48 1.91 2.14 2.48 ns lvcmos12, fast, 2 ma 0.84 0.96 1.14 3.05 3.38 3.87 3.05 3.38 3.87 ns lvcmos12, fast, 4 ma 0.84 0.96 1.14 1.71 1.91 2.20 1.71 1.91 2.20 ns lvcmos12, fast, 6 ma 0.84 0.96 1.14 1.58 1.78 2.08 1.58 1.78 2.08 ns lvcmos12, fast, 8 ma 0.84 0.96 1.14 1.52 1.70 1.97 1.52 1.70 1.97 ns lvdci_33 0.62 0.70 0.82 1.50 1.66 1.90 1.50 1.66 1.90 ns lvdci_25 0.61 0.70 0.82 1.55 1.71 1.93 1.55 1.71 1.93 ns lvdci_18 0.67 0.76 0.89 1.65 1.78 1.99 1.65 1.78 1.99 ns lvdci_15 0.73 0.83 0.98 1.58 1.75 2.02 1.58 1.75 2.02 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -3 -2 -1 -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 35 lvdci_dv2_25 0.61 0.70 0.82 1.36 1.51 1.74 1.36 1.51 1.74 ns lvdci_dv2_18 0.67 0.76 0.89 1.43 1.60 1.85 1.43 1.60 1.85 ns lvdci_dv2_15 0.73 0.83 0.98 1.48 1.65 1.91 1.48 1.65 1.91 ns gtl_dci 0.76 0.85 1.00 1.36 1.47 1.65 1.36 1.47 1.65 ns gtlp_dci 0.76 0.85 1.00 1.37 1.52 1.76 1.37 1.52 1.76 ns lvpecl_25 0.80 0.90 1.06 1.28 1.42 1.62 1.28 1.42 1.62 ns hstl_i_12 0.76 0.85 1.00 1.45 1.61 1.85 1.45 1.61 1.85 ns hstl_i_dci 0.76 0.85 1.00 1. 41 1.56 1.77 1.41 1.56 1.77 ns hstl_ii_dci 0.76 0.85 1.00 1. 34 1.48 1.69 1.34 1.48 1.69 ns hstl_ii_t_dci 0.76 0.85 1.00 1. 41 1.56 1.77 1.41 1.56 1.77 ns hstl_iii_dci 0.76 0.85 1.00 1. 57 1.72 1.95 1.57 1.72 1.95 ns hstl_iv_dci 0.76 0.85 1.00 1. 34 1.46 1.64 1.34 1.46 1.64 ns hstl_i_dci_18 0.76 0.85 1.00 1.36 1.50 1.70 1.36 1.50 1.70 ns hstl_ii_dci_18 0.76 0.85 1.00 1. 30 1.43 1.64 1.30 1.43 1.64 ns hstl_ii _t_dci_18 0.76 0.85 1.0 0 1.36 1.50 1.70 1.36 1.50 1.70 ns hstl_iii_dci_18 0.76 0.85 1.00 1 .55 1.69 1.91 1.55 1.69 1.91 ns hstl_iv_dci_18 0.76 0.85 1.00 1.31 1.44 1.62 1.31 1.44 1.62 ns diff_hstl_i_18 0.80 0.90 1.06 1.40 1.55 1.77 1.40 1.55 1.77 ns diff_hstl_i_dci_18 0.80 0.90 1.0 6 1.36 1.50 1.70 1.36 1.50 1.70 ns diff_hstl_i 0.80 0.90 1.06 1. 42 1.57 1.79 1.42 1.57 1.79 ns diff_hstl_i_dci 0.80 0.90 1.06 1.41 1.56 1.77 1.41 1.56 1.77 ns diff_hstl_ii_18 0.80 0.90 1.06 1.36 1.51 1.72 1.36 1.51 1.72 ns diff_hstl_ii_dci_18 0.80 0.90 1.06 1.30 1.43 1.64 1.30 1.43 1.64 ns diff_hstl_ii 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns diff_hstl_ii_dci 0.80 0.90 1.06 1.34 1.48 1.69 1.34 1.48 1.69 ns sstl2_i_dci 0.76 0.85 1.00 1. 42 1.56 1.78 1.42 1.56 1.78 ns sstl2_ii_dci 0.76 0.85 1.00 1. 34 1.48 1.70 1.34 1.48 1.70 ns sstl2_ii_t_dci 0.76 0.85 1.00 1. 42 1.56 1.78 1.42 1.56 1.78 ns sstl18_i 0.76 0.85 1.00 1.46 1.61 1.84 1.46 1.61 1.84 ns sstl18_ii 0.76 0.85 1.00 1.39 1.53 1.75 1.39 1.53 1.75 ns sstl18_i_dci 0.76 0.85 1.00 1. 39 1.53 1.74 1.39 1.53 1.74 ns sstl18_ii_dci 0.76 0.85 1.00 1. 30 1.44 1.64 1.30 1.44 1.64 ns sstl18_ii_t_dci 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -3 -2 -1 -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 36 diff_sstl2_i 0.80 0.90 1.06 1. 48 1.64 1.87 1.48 1.64 1.87 ns diff_sstl2_i_dci 0.80 0.90 1.06 1.42 1.56 1. 78 1.42 1.56 1.78 ns diff_sstl18_i 0.80 0.90 1.06 1.46 1.61 1.84 1.46 1.61 1.84 ns diff_sstl18_i_dci 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns diff_sstl2_ii 0.80 0.90 1.06 1.40 1.55 1.76 1.40 1.55 1.76 ns diff_sstl2_ii_dci 0.80 0.90 1.06 1.34 1.48 1.70 1.34 1.48 1.70 ns diff_sstl18_ii 0.80 0.90 1.06 1. 39 1.53 1.75 1.39 1.53 1.75 ns diff_sstl18_ii_dci 0. 80 0.90 1.06 1.30 1.44 1.64 1.30 1.44 1.64 ns ta bl e 5 7 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -3 -2 -1 t iotphz t input to pad high-impedance 0.88 1.01 1.12 ns ta bl e 5 6 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -3 -2 -1 -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 37 i/o standard adjustment measurement methodology input delay measurements ta bl e 5 8 shows the test setup parameters used for measuring input delay. ta bl e 5 8 : input delay measurement methodology description i/o standard attribute v l (1,2) v h (1,2) v meas (1,4,5) v ref (1,3,5) lvttl (low-voltage transistor-transistor logic) lvttl 0 3.0 1.4 ? lvcmos (low-voltage cmos), 3.3v lvcmos33 0 3.3 1.65 ? lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? lvcmos, 1.2v lvcmos12 0 1.2 0.6 ? pci (peripheral component interconnect), 33 mhz, 3.3v pci33_3 per pci? specification ? pci, 66 mhz, 3.3v pci66_3 per pci specification ? pci-x, 133 mhz, 3.3v pcix per pci-x? specification ? gtl (gunning transceiver logic) gtl v ref ?0.2 v ref +0.2 v ref 0.80 gtl plus gtlp v ref ?0.2 v ref +0.2 v ref 1.0 hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii & iv hstl_iii, hstl_iv v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii & iv, 1.8v hstl_iii_18, hstl_iv_18 v ref ?0.5 v ref +0.5 v ref 1.08 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?1.00 v ref +1.00 v ref 1.5 sstl, class i & ii, 2.5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 agp-2x/agp (accelerated graphics port) agp v ref ?(0.2xv cco )v ref +(0.2xv cco )v ref agp spec lvds (low-voltage differential signal ing), 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) lvdsext (lvds extended mode), 2.5v lvdsext_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ldt (hypertransport), 2.5v ldt_25 0.6 ? 0.125 0.6 + 0.125 0 (6) lvpecl (low-voltage positive emitter-coupled logic), 2.5v lvpecl_25 1.15 ? 0.3 1.15 ? 0.3 0 (6) notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input delay measurement methodology parameters for hslvdci are the same as fo r hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect wors t case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 11 . 6. the value given is the differential input voltage.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 38 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4? of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4? trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 11 and figure 12 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 5 9 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 11 figure 11: single ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 202_06_11160 8 x-ref target - figure 12 figure 12: differential test setup r ref v meas + ? c ref fpga output ds202_12_042808 ta bl e 5 9 : output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvttl (low-voltage transistor-transistor logic) lvttl (all) 1m 0 1.4 0 lvcmos (low-voltage cmos), 3.3v lvcmos33 1m 0 1.65 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.6 0 pci (peripheral component interface), 33 mhz, 3.3v pci33_3 (rising edge) 25 10 (2) 0.94 0 pci33_3 (falling edge) 25 10 (2) 2.03 3.3 pci, 66 mhz, 3.3v pci66_3 (rising edge) 25 10 (2) 0.94 0 pci66_3 (falling edge) 25 10 (2) 2.03 3.3 pci-x, 133 mhz, 3.3v pcix (rising edge) 25 10 (3) 0.94 pcix (falling edge 25 10 (3) 2.03 3.3 gtl (gunning transceiver logic) gtl 25 0 0.8 1.2 gtl plus gtlp 25 0 1.0 1.5 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 39 hstl, class iv hstl_iv 25 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 hstl, class iv, 1.8v hstl_iv_18 25 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25 sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 lvds (low-voltage differential signaling), 2.5v lvds_25 100 0 0 (4) 1.2 lvdsext (lvds extended mode), 2.5v lvds_25 100 0 0 (4) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (4) 0 ldt (hypertransport), 2.5v ldt_25 100 0 0 (4) 0.6 lvpecl (low-voltage positi ve emitter-coupled logic), 2.5v lvpecl_25 100 0 0 (4) 0 lvdci/hslvdci (low-voltage digitally controlled impedance), 3.3v lvdci_33, hslvdci_33 1m 0 1.65 0 lvdci/hslvdci, 2.5v lvdci_25, hslvdci_25 1m 0 1.25 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0 hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class iii & iv, with dci hstl_iii_dci, hstl_iv_dci 50 0 0.9 1.5 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 hstl, class iii & iv, 1.8v, with dci hstl_iii_dci_18, hstl_iv_dci_18 50 0 1.1 1.8 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl, class i & ii, 2.5v, with dci sstl2_i_dci, sstl2_ii_dci 50 0 v ref 1.25 gtl (gunning transceiver logic) with dci gtl_dci 50 0 0.8 1.2 gtl plus with dci gtlp_dci 50 0 1.0 1.5 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. per pci specifications. 3. per pci-x specifications. 4. the value given is the differential input voltage. ta bl e 5 9 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v)
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 40 input/output logic switching characteristics ta bl e 6 0 : ilogic switching characteristics symbol description speed grade units -3 -2 -1 setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to clk 0.43 ?0.24 0.49 ?0.24 0.59 ?0.24 ns t isrck /t icksr sr/rev pin setup/hold with respect to clk 0.85 ?0.20 1.00 ?0.20 1.22 ?0.20 ns t idock /t iockd d pin setup/hold with respect to clk without delay 0.34 ?0.12 0.37 ?0.12 0.39 ?0.12 ns t idockd /t iockdd ddly pin setup/hold with respec t to clk (using iodelay) 0.31 ?0.09 0.33 ?0.09 0.36 ?0.08 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.24 0.26 0.30 ns t idid ddly pin to o pin propagation delay (using iodelay) 0.20 0.22 0.26 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.44 0.50 0.58 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using iodelay) 0.41 0.46 0.55 ns t ickq clk to q outputs 0.47 0.52 0.60 ns t rq sr/rev pin to oq/tq out 1.12 1.28 1.53 ns t gsrq global set/reset to q outputs 7.30 7.30 10.10 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.78 0.95 1.20 ns, min
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 41 ta bl e 6 1 : ologic switching characteristics symbol description speed grade units -3 -2 -1 setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.30 ?0.21 0.36 ?0.21 0.44 ?0.21 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.16 ?0.07 0.19 ?0.07 0.23 ?0.07 ns t osrck /t ocksr sr/rev pin setup/hold with respect to clk 0.93 ?0.20 1.02 ?0.20 1.16 ?0.20 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0.28 ?0.18 0.34 ?0.18 0.41 ?0.18 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.20 ?0.06 0.23 ?0.06 0.29 ?0.06 ns combinatorial t doq d1 to oq out or t1 to tq out 0.62 0.70 0.83 ns sequential delays t ockq clk to oq/tq out 0.61 0.62 0.62 ns t rq sr/rev pin to oq/tq out 1.63 1.89 2.27 ns t gsrq global set/reset to q outputs 7.30 7.30 10.10 ns set/reset t rpw minimum pulse width, sr/rev inputs 0.80 0.98 1.25 ns, min
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 42 input serializer/deserializer switching characteristics ta bl e 6 2 : iserdes switching characteristics symbol description speed grade units -3 -2 -1 setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.10 0.00 0.11 0.00 0.12 0.00 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.43 ?0.24 0.49 ?0.24 0.59 ?0.24 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.03 0.11 0.04 0.13 0.06 0.15 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk 0.34 ?0.12 0.37 ?0.12 0.39 ?0.12 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using iodelay) 0.31 ?0.09 0.33 ?0.09 0.36 ?0.08 ns t isdck_ddr /t isckd_ddr d pin setup/hold with respect to clk at ddr mode 0.34 ?0.12 0.37 ?0.12 0.39 ?0.12 ns t isdck_ddly_ddr t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using iodelay) 0.31 ?0.09 0.33 ?0.09 0.36 ?0.08 ns sequential delays t iscko_q clkdiv to out at q pin 0.46 0.51 0.60 ns propagation delays t isdo_do d input to do output pin 0.20 0.22 0.26 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in trace report.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 43 output serializer/deserializ er switching characteristics ta bl e 6 3 : oserdes switching characteristics symbol description speed grade units -3 -2 -1 setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv 0.21 ?0.02 0.24 ?0.02 0.30 ?0.02 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0.28 ?0.18 0.34 ?0.18 0.41 ?0.18 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.21 ?0.03 0.24 ?0.03 0.28 ?0.03 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.16 ?0.07 0.19 ?0.07 0.23 ?0.07 ns t oscck_s sr (reset) input setup with re spect to clkdiv 0.52 0.58 0.70 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.20 ?0.06 0.23 ?0.06 0.29 ?0.06 ns sequential delays t oscko_oq clock to out from clk to oq 0.59 0.60 0.61 ns t oscko_tq clock to out from clk to tq 0.61 0.62 0.62 ns combinatorial t osdo_ttq t input to tq out 0.62 0.70 0.83 ns t osco_oq asynchronous reset to oq 1.57 1.82 2.19 ns t osco_tq asynchronous reset to tq 1.63 1.89 2.27 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in trace report.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 44 input/output delay swit ching characteristics clb switching characteristics ta bl e 6 4 : input/output delay switching characteristics symbol description speed grade units -3 -2 -1 idelayctrl t idelayctrlco_rdy reset to ready for idelayctrl 3.00 3.00 3.00 s f idelayctrl_ref refclk frequency 200.00 200.00 200.00 mhz idelayctrl_ref_precision refclk precision 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 50.00 50.00 50.00 ns iodelay t idelayresolution iodelay chain delay resolution 1/(64 x f ref x1e 6 ) (1) ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern 000note2 pattern dependent period jitter in delay chain for random data pattern (prbs 23) 5 5 5 note 2 t iodelay_clk_max maximum frequency of clk input to iodelay 300 250 250 mhz t iodcck_ce / t iodckc_ce ce pin setup/hold with respect to ck 0.29 ?0.06 0.34 ?0.06 0.42 ?0.06 ns t iodck_inc / t iodckc_inc inc pin setup/hold with respect to ck 0.18 0.02 0.20 0.04 0.24 0.06 ns t iodck_rst / t iodckc_rst rst pin setup/hold with respect to ck 0.25 ?0.12 0.28 ?0.12 0.33 ?0.12 ns t ioddo_t tscontrol delay to muxe/muxf switching and through iodelay note 3 note 3 note 3 t ioddo_idatain propagation delay through iodelay note 3 note 3 note 3 t ioddo_odatain propagation delay through iodelay note 3 note 3 note 3 notes: 1. average tap delay at 200 mhz = 78 ps. 2. units in ps, peak-to-peak per tap, in high performance mode. 3. delay depends on iodelay tap setting. see trace report for actual values. ta bl e 6 5 : clb switching characteristics symbol description speed grade units -3 -2 -1 combinatorial delays t ilo an ? dn lut address to a 0.08 0.09 0.10 ns, max an ? dn lut address to amux/cmux 0.20 0.22 0.25 ns, max an ? dn lut address to bmux_a 0.31 0.35 0.40 ns, max t ito an ? dn inputs to a ? d q outputs 0.67 0.77 0.90 ns, max t axa ax inputs to amux output 0.39 0.44 0.53 ns, max t axb ax inputs to bmux output 0.46 0.52 0.61 ns, max t axc ax inputs to cmux output 0.31 0.36 0.42 ns, max t axd ax inputs to dmux output 0.55 0.62 0.73 ns, max t bxb bx inputs to bmux output 0.36 0.41 0.48 ns, max t bxd bx inputs to dmux output 0.45 0.51 0.59 ns, max
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 45 t cxb cx inputs to cmux output 0.33 0.36 0.42 ns, max t cxd cx inputs to dmux output 0.37 0.42 0.49 ns, max t dxd dx inputs to dmux output 0.38 0.42 0.49 ns, max t opcya an input to cout out put 0.43 0.50 0.59 ns, max t opcyb bn input to cout out put 0.39 0.44 0.51 ns, max t opcyc cn input to cout output 0.33 0.37 0.43 ns, max t opcyd dn input to cout output 0.30 0.34 0.40 ns, max t axcy ax input to cout output 0.36 0.42 0.50 ns, max t bxcy bx input to cout output 0.26 0.30 0.37 ns, max t cxcy cx input to cout outp ut 0.20 0.22 0.26 ns, max t dxcy dx input to cout outp ut 0.20 0.22 0.26 ns, max t byp cin input to cout output 0.09 0.10 0.11 ns, max t cina cin input to amux output 0.24 0.27 0.31 ns, max t cinb cin input to bmux output 0.27 0.30 0.35 ns, max t cinc cin input to cmux output 0.29 0.32 0.36 ns, max t cind cin input to dmux output 0.31 0.35 0.41 ns, max sequential delays t cko clock to aq ? dq outputs 0.35 0.40 0.47 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick /t ckdi ax ? dx input to clk on a ? d flip flops 0.36 0.19 0.41 0.21 0.49 0.24 ns, min t rck dx input to clk when used as rev 0.37 0.42 0.51 ns, min t ceck /t ckce ce input to clk on a ? d flip flops 0.18 ?0.04 0.20 ?0.04 0.23 ?0.04 ns, min t srck /t cksr sr input to clk on a ? d flip flops 0.41 ?0.19 0.49 ?0.19 0.59 ?0.19 ns, min t cinck /t ckcin cin input to clk on a ? d flip flops 0.14 0.14 0.16 0.16 0.18 0.19 ns, min set/reset t srmin sr input minimum pulse width 0.90 0.90 0.90 ns, min t rq delay from sr or rev input to aq ? dq flip-flops 0.74 0.86 1.03 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.46 0.52 0.63 ns, max f tog toggle frequency (for export control) 1412 1265 1098 mhz notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications. ta bl e 6 5 : clb switching characteristics (cont?d) symbol description speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 46 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) ta bl e 6 6 : clb distributed ram swit ching characteristics symbol description speed grade units -3 -2 -1 sequential delays t shcko clock to a ? b outputs 1.08 1.26 1.54 ns, max t shcko_1 clock to amux ? bmux outputs 1.19 1.38 1.68 ns, max setup and hold times before/after clock clk t ds /t dh a ? d inputs to clk 0.72 0.20 0.84 0.22 1.03 0.26 ns, min t as /t ah address an inputs to clock 0.41 0.20 0.46 0.22 0.54 0.27 ns, min t ws /t wh we input to clock 0.34 ?0.06 0.39 ?0.04 0.46 ?0.02 ns, min t ceck /t ckce ce input to clk 0.36 ?0.08 0.42 ?0.07 0.51 ?0.06 ns, min clock clk t mpw minimum pulse width 0.70 0.82 1.00 ns, min t mcp minimum clock period 1.40 1.64 2.00 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. tshcko also represents the clk to xmux output. refer to trace report for the clk to xmux path. ta bl e 6 7 : clb shift register switching characteristics symbol description speed grade units -3 -2 -1 sequential delays t reg clock to a ? d outputs 1.23 1.43 1.73 ns, max t reg_mux clock to amux ? dmux output 1.33 1.55 1.87 ns, max t reg_m31 clock to dmux output via m31 output 0.99 1.15 1.38 ns, max setup and hold times before/after clock clk t ws /t wh we input 0.21 ?0.06 0.24 ?0.04 0.29 ?0.02 ns, min t ceck /t ckce ce input to clk 0.23 ?0.08 0.27 ?0.07 0.33 ?0.06 ns, min t ds /t dh a ? d inputs to clk 0.57 0.07 0.66 0.09 0.78 0.11 ns, min clock clk t mpw minimum pulse width 0.60 0.70 0.85 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 47 block ram and fifo switching characteristics ta bl e 6 8 : block ram and fifo switching characteristics symbol description speed grade units -3 -2 -1 block ram and fifo clock to out delays t rcko_do and t rcko_dor (1) clock clk to dout ou tput (without output register) (2,3) 1.79 1.92 2.19 ns, max clock clk to dout output (with output register) (4,5) 0.61 0.69 0.82 ns, max clock clk to dout output with ecc (without output register) (2,3) 2.64 3.03 3.61 ns, max clock clk to dout output with ecc (with output register) (4,5) 0.66 0.77 0.93 ns, max clock clk to dout output with cascade (without output register) (2) 2.10 2.44 2.94 ns, max clock clk to dout output with cascade (with output register) (4) 0.91 1.07 1.30 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.76 0.87 1.02 ns, max t rcko_pointers clock clk to fifo pointer outputs (7) 1.10 1.26 1.48 ns, max t rcko_eccr clock clk to biterr (with output register) 0.66 0.77 0.93 ns, max t rcko_ecc clock clk to biterr (without out put register) 2.48 2.85 3.41 ns, max clock clk to eccparity in stan dard ecc mode 1.29 1.47 1.74 ns, max clock clk to eccparity in ecc encode only mode 0.77 0.89 1.05 ns, max setup and hold times before/after clock clk t rcck_addr /t rckc_addr addr inputs (8) 0.34 0.30 0.40 0.32 0.48 0.36 ns, min t rdck_di /t rckd_di din inputs (9) 0.27 0.28 0.30 0.28 0.35 0.29 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with ecc in standard mode (9) 0.33 0.32 0.37 0.33 0.42 0.36 ns, min din inputs with ecc encode only (9 0.68 0.32 0.72 0.33 0.77 0.36 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.32 0.15 0.36 0.15 0.42 0.15 ns, min t rcck_regce /t rckc_regce ce input of out put register 0.15 0.22 0.16 0.24 0.18 0.27 ns, min t rcck_ssr /t rckc_ssr synchronous set/ reset (ssr) input 0.17 0.23 0.21 0.25 0.26 0.28 ns, min t rcck_we /t rckc_we write enable (we) input 0.44 0.16 0.51 0.17 0.63 0.18 ns, min t rcck_wren /t rckc_wren wren/rden fifo inputs (10) 0.36 0.30 0.41 0.34 0.48 0.40 ns, min
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 48 dsp48e switching characteristics reset delays t rco_flags reset rst to fifo flags/pointers (11) 1.10 1.26 1.48 ns, max maximum frequency f max block ram in all modes 550 500 450 mhz f max_cascade block ram in cascade configuration 500 450 400 mhz f max_fifo fifo in all modes 550 500 450 mhz f max_ecc block ram and fifo in ecc configuration 415 375 325 mhz notes: 1. trace will report all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to sy nchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asy nchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted even though we is deasserted. otherwise, block ram data corruption is p ossible. 9. t rcko_di includes both a and b inputs as we ll as the parity inputs of a and b. 10. these parameters also apply to rden. 11. t rco_flags includes the following flags: aempty, afull, empty, full, rderr, wrerr, rdcount, and wrcount. ta bl e 6 9 : dsp48e switching characteristics symbol description speed units -3 -2 -1 setup and hold times of data/control pins to the input register clock tdspdck_{aa, bb, acina, bcinb}/ tdspckd_{aa, bb, acina, bcinb} {a, b, acin, bcin} input to {a, b} register clk 0.17 0.17 0.21 0.23 0.26 0.30 ns tdspdck_cc/tdspckd_cc c input to c register clk 0.14 0.26 0.16 0.31 0.20 0.37 ns setup and hold times of data pins to the pipeline register clock tdspdck_{am, bm, acinm, bcinm}/ tdspckd_{am, bm, acinm, bcinm} {a, b, acin, bcin} input to m register clk 1.30 0.19 1.44 0.19 1.71 0.19 ns setup and hold times of data/control pins to the output register clock tdspdck_{ap, bp, acinp, bcinp}_m/ tdspckd_{ap, bp, acinp, bcinp}_m {a, b, acin, bcin} input to p register clk using multiplier 2.39 ?0.30 2.74 ?0.30 3.25 ?0.30 ns tdspdck_{ap, bp, acinp, bcinp}_nm/ tdspckd_{ap, bp, acinp, bcinp}_nm {a, b, acin, bcin} input to p register clk not using multiplier 1.35 ?0.10 1.54 ?0.10 1.83 ?0.10 ns tdspdck_cp/tdspckd_cp c input to p register clk 1.30 ?0.13 1.42 ?0.13 1.70 ?0.13 ns tdspdck_{pcinp, crycinp, multsigninp}/ tdspckd_{pcinp, crycinp, multsigninp} {pcin, carrycascin, multsignin} input to p register clk 1.06 0.11 1.17 0.11 1.31 0.11 ns setup and hold times of the ce pins tdspcck_{cea1a, cea2a, ceb1b, ceb2b}/ tdspckc_{cea1a, cea2 a, ceb1a, ceb2b} {cea1, cea2a, ceb1b, ceb2b} input to {a, b} register clk 0.24 0.21 0.28 0.25 0.33 0.31 ns tdspcck_cecc/tdspckc_cecc cec input to c register clk 0.19 0.17 0.21 0.21 0.26 0.28 ns ta bl e 6 8 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 49 tdspcck_cemm/tdspckc_cemm cem input to m register clk 0.25 0.18 0.29 0.21 0.36 0.26 ns tdspcck_cepp/tdspckc_cepp cep in put to p register clk 0.56 0.01 0.63 0.01 0.73 0.01 ns setup and hold times of the rst pins tdspcck_{rstaa, rstbb}/ tdspckc_{rstaa, rstbb} {rsta, rstb} input to {a, b} register clk 0.24 0.23 0.28 0.26 0.33 0.31 ns tdspcck_rstcc/ tdspckc_rstcc rstc input to c register clk 0.19 0.17 0.21 0.21 0.26 0.28 ns tdspcck_rstmm/ tdspckc_rstmm rstm input to m register clk 0.25 0.18 0.29 0.21 0.36 0.26 ns tdspcck_rstpp/tdspckc_rstpp rstp input to p register clk 0.56 0.01 0.63 0.01 0.73 0.01 ns combinatorial delays from input pins to output pins tdspdo_{ap, acryout, bp, bcryout}_m {a, b} input to {p, carryout} output using multiplier 2.78 3.22 3.84 ns tdspdo_{ap, acryout, bp, bcryout}_nm {a, b} input to {p, carryout} output not using multiplier 1.59 1.77 2.22 ns tdspdo_{cp, ccryout, cryinp, cryincryout} {c, carryin} input to {p, carryout} output 1.50 1.67 2.08 ns combinatorial delays from input pins to cascading output pins tdspdo_{aacout, bbcout} {a, b} input to {acout, bcout} output 1.00 1.12 1.31 ns tdspdo_{apcout, acrycout, amultsignout, bpcout, bcrycout, bmultsignout}_m {a, b} input to {pcout, carrycascout, multsignout} output using multiplier 2.78 3.22 3.84 ns tdspdo_{apcout, acrycout, amultsignout, bpcout, bcrycout, bmultsignout}_nm {a, b} input to {pcout, carrycascout, multsignout} output not using multiplier 1.72 1.92 2.42 ns tdspdo_{cpcout, ccrycout, cmultsignout, cryinpcout, cryincrycout, cryinmultsignout} {c, carryin} input to {pcout, carrycascout, multsignout} output 1.63 1.82 2.28 ns combinatorial delays from cascading input pins to all output pins tdspdo_{acinp, acincryout, bcinp, bcincryout}_m {acin, bcin} input to {p, carryout} output using multiplier 2.78 3.22 3.84 ns tdspdo_{acinp, acincryout, bcinp, bcincryout}_nm {acin, bcin} input to {p, carryout} output not using multiplier 1.59 1.77 2.22 ns tdspdo_{acinacout, bcinbcout} {acin, bcin} input to {acout, bcout} output 1.00 1.12 1.31 ns tdspdo_{acinpcout, acincrycout, acinmultsignout, bcinpcout, bcincrycout, bcinmultsignout}_m {acin, bcin} input to {pcout, carrycascout, multsignout} output using multiplier 2.78 3.22 3.84 ns tdspdo_{acinpcout, acincrycout, acinmultsignout, bcinpcout, bcincrycout, bcinmultsignout}_nm {acin, bcin} input to {pcout, carrycascout, multsignout} output not using multiplier 1.72 1.92 2.42 ns tdspdo_{pcinp, crycinp, multsigninp, pcincryout, crycincryout, multsignincryout} {pcin, carrycascin, multsignin} input to {p, carryout} output 1.30 1.45 1.82 ns ta bl e 6 9 : dsp48e switching characteristics (cont?d) symbol description speed units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 50 tdspdo_{pcinpcout, crycinpcout, multsigninpcout, pcincrycout, crycincrycout, multsignincrycout, pcinmultsignout, crycinmultsignout, multsigninmultsignout} {pcin, carrycascin, multsignin} input to {pcout, carrycascout, multsignout} output 1.43 1.60 2.02 ns clock to outs from output re gister clock to output pins tdspcko_{pp, cryoutp} clk (preg) to {p, carryout} output 0.45 0.48 0.56 ns tdspcko_{crycoutp, pcoutp, multsignoutp} clk (preg) to {carrycascout, pcout, multsignout} output 0.48 0.53 0.62 ns clock to outs from pipeline register clock to output pins tdspcko_{pm, cryoutm} clk (mreg) to {p, carryout} output 1.81 2.10 2.47 ns tdspcko_{pcoutm, crycoutm, multsignoutm} clk (mreg) to {pcout, carrycascout, multsignout} output 1.91 2.13 2.66 ns clock to outs from input re gister clock to output pins tdspcko_{pa, cryouta, pb, cryoutb}_m clk (areg, breg) to {p, carryout} output using multiplier 3.09 3.57 4.23 ns tdspcko_{pa, cryouta, pb, cryoutb}_nm clk (areg, breg) to {p, carryout} output not using multiplier 1.90 2.11 2.63 ns tdspcko_{pc, cryoutc} clk (creg) to {p, carryout} output 1.89 2.11 2.62 ns clock to outs from input register clock to cascadi ng output pins tdspcko_{acouta, bcoutb} clk (areg, breg) to {acout, bcout} 0.61 0.68 0.79 ns tdspcko_{pcouta, crycouta, multsignouta, pcoutb, crycoutb, multsignoutb}_m clk (areg, breg) to {pcout, carrycascout, multsignout} output using multiplier 3.09 3.57 4.23 ns tdspcko_{pcouta, crycouta, multsignouta, pcoutb, crycoutb, multsignoutb}_nm clk (areg, breg) to {pcout, carrycascout, multsignout} output not using multiplier 2.03 2.27 2.82 ns tdspcko_{pcoutc, crycoutc, multsi gnoutc} clk (creg) to {pcout, carrycascout, multsignout} output 2.03 2.26 2.82 ns maximum frequency f max with all registers used 550 500 450 mhz f max_patdet with pattern detector 515 465 410 mhz f max_mult_nomreg two register multiply without mreg 374 324 275 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 345 300 254 mhz ta bl e 6 9 : dsp48e switching characteristics (cont?d) symbol description speed units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 51 configuration switching characteristics ta bl e 7 0 : configuration switching characteristics symbol description speed grade units -3 -2 -1 power-up timing characteristics t pl program latency 3 3 3 ms, max t por power-on-reset 10 50 10 50 10 50 ms, min/max t icck cclk (output) delay 400 400 400 ns, min t program program pulse width 250 250 250 ns, min master/slave serial mode programming switching (1) t dcck /t cckd din setup/hold, slave mode 4.0 0.0 4.0 0.0 4.0 0.0 ns, min t dscck /t scckd din setup/hold, master mode 4.0 0.0 4.0 0.0 4.0 0.0 ns, min t cco dout 7.5 7.5 7.5 ns, max f mcck maximum frequency, master mode with respect to nominal cclk. 100 100 100 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk. 50 50 50 % f mscck slave mode external cclk 100 100 100 mhz selectmap mode programming switching (1) t smdcck /t smcckd selectmap data setup/hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, min t smcscck /t smcckcs cs_b setup/hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, min t smcckw /t smwcck rdwr_b setup/hold 8.0 0.5 8.0 0.5 8.0 0.5 ns, min t smckcso cso_b clock to out (330 pull-up resistor required) 10 10 10 ns, min t smco cclk to data out in readback 9.0 9.0 9.0 ns, max t smckby cclk to busy out in readback 7.5 7.5 7.5 ns, max f smcck maximum frequency with respect to nominal cclk. 100 100 100 mhz, max f rbcck maximum readback frequency with respect to nominal cclk 60 60 60 mhz, max f mccktol frequency tolerance with respect to nominal cclk. 50 50 50 % boundary-scan port timing specifications t taptck tms and tdi setup time before tck 1.0 1.0 1.0 ns, min t tcktap tms and tdi hold time after tck 2.0 2.0 2.0 ns, min t tcktdo tck falling edge to tdo output valid 6 6 6 ns, max f tck maximum configuration tck clock frequency 66 66 66 mhz, max f tckb maximum boundary-scan tck clock frequency 66 66 66 mhz, max
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 52 bpi master flash mode programming switching t bpicco (4) addr[25:0], rs[1:0], fcs_b, foe_b, fwe_b outputs valid after cclk rising edge 10 10 10 ns t bpidcc /t bpiccd setup/hold on d[15:0] data input pins 3.0 0.5 3.0 0.5 3.0 0.5 ns t initaddr minimum period of init ial addr[25:0] address cycles 3.0 3.0 3.0 cclk cycles spi master flash mode programming switching t spidcc /t spidccd din setup/hold before/after the rising cclk edge 4.0 0.0 4.0 0.0 4.0 0.0 ns t spiccm mosi clock to out 10 10 10 ns t spiccfc fcs_b clock to out 10 10 10 ns t fsinit /t fsinith fs[2:0] to init_b rising edge setup and hold 2 2 2 s cclk output (master modes) t mcckl master cclk clock minimum low time 3.0 3.0 3.0 ns, min t mcckh master cclk clock minimum high time 3.0 3.0 3.0 ns, min cclk input (slave modes) t scckl slave cclk clock minimum low time 2.0 2.0 2.0 ns, min t scckh slave cclk clock minimum high time 2.0 2.0 2.0 ns, min dynamic reconfiguration port (drp) for dcm and pll before and after dclk f dck maximum frequency for dclk 500 450 400 mhz t dmcck_daddr /t dmckc_daddr daddr setup/hold 1.2 0.0 1.35 0.0 1.56 0.0 ns t dmcck_di /t dmckc_di di setup/hold 1.2 0.0 1.35 0.0 1.56 0.0 ns t dmcck_den /t dmckc_den den setup/hold time 1.2 0.0 1.35 0.0 1.56 0.0 ns t dmcck_dwe /t dmckc_dwe dwe setup/hold time 1.2 0.0 1.35 0.0 1.56 0.0 ns t dmcko_do clk to out of do (3) 1.0 1.12 1.3 ns t dmcko_drdy clk to out of drdy 1.0 1.12 1.3 ns notes: 1. maximum frequency and setup/hold timing parameters are for 3.3v and 2.5v configuration voltages. 2. to support longer delays in configuration, use the design solutions described in ug190 : virtex-5 fpga user guide . 3. do will hold until next drp operation. 4. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. ta bl e 7 0 : configuration switching characteristics (cont?d) symbol description speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 53 clock buffers and networks ta bl e 7 1 : global clock switching characte ristics (incl uding bufgctrl) symbol description devices speed grade units -3 -2 -1 t bccck_ce /t bcckc_ce (1) ce pins setup/hold all 0.27 0.00 0.27 0.00 0.31 0.00 ns t bccck_s /t bcckc_s (1) s pins setup/hold all 0.27 0.00 0.27 0.00 0.31 0.00 ns t bccko_o (2) bufgctrl delay from i0/i1 to o lx20t n/a 0.24 0.30 ns lx30, lx30t, lx50, lx50t, lx85, lx85t, lx110, lx110t, sx35t, sx50t, fx70t, fx100t, and fx130t 0.19 0.22 0.25 ns fx30t 0.23 0.23 0.25 ns lx155 and lx155t 0.12 0.14 0.30 ns lx220, lx220t, lx330, lx330t, sx95t, sx240t, tx150t, tx240t, and fx200t n/a 0.22 0.25 ns maximum frequency f max global clock tree (bufg) lx20t n/a 667 600 mhz lx30, lx30t, lx50, lx50t, lx85, lx85t, lx110, lx110t, sx35t, sx50t, fx30t, and fx70t 710 667 600 mhz lx155, lx155t, and fx100t 650 600 550 mhz fx130t 550 500 450 mhz lx220, lx220t, lx330, lx330t, sx95t, sx240t, tx150t, tx240t, and fx200t n/a 500 450 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glitch-free operation. the other global clock setup and h old times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when swit ching between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 7 2 : input/output clock switching characteristics (bufio) symbol description speed grade units -3 -2 -1 t bufiocko_o clock to out delay from i to o 1.08 1.16 1.29 ns maximum frequency f max i/o clock tree (bufio) 710 710 644 mhz
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 54 ta bl e 7 3 : regional clock switching characteristics (bufr) symbol description devices speed grade units -3 -2 -1 t brcko_o clock to out delay from i to o lx20t n/a 0.79 0.90 ns lx30, lx30t, lx50, lx50t, lx85, lx85t, lx110, lx110t, sx35t, sx50t, fx100t, and fx130t 0.56 0.59 0.67 ns fx30t 0.72 0.78 0.86 ns fx70t 0.69 0.74 0.83 ns lx155 and lx155t 0.73 0.80 0.90 ns lx220, lx220t, lx330, lx330t, sx95t, sx240t, tx150t, tx240t, and fx200t n/a 0.59 0.67 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set lx20t n/a 0.29 0.30 ns lx30, lx30t, lx50, lx50t, lx85, lx85t, lx110, lx110t, sx35t, sx50t, fx30t, fx70t, fx100t, and fx130t 0.23 0.24 0.26 ns lx155 and lx155t 0.24 0.26 0.30 ns lx220, lx220t, lx330, lx330t, sx95t, sx240t, tx150t, tx240t, and fx200t n/a 0.24 0.26 ns t brdo_clro propagation delay from clr to o all 0.61 0.70 0.82 ns maximum frequency f max regional clock tree (bufr) all 300 250 250 mhz
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 55 pll switching characteristics ta bl e 7 4 : pll specification symbol description speed grade units -3 -2 -1 f inmax maximum input clock frequency 710 710 645 mhz f inmin minimum input clock frequency 19 19 19 mhz f injitter maximum input clock period jitter <20% of clock input period or 1 ns max f induty allowable input duty cycle: 19?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % f vcomin minimum pll vco frequency 400 400 400 mhz f vcomax maximum pll vco frequency 1440 1200 1000 mhz f bandwidth low pll bandwidth at typical (1) 111mhz high pll bandwidth at typical (1) 444mhz t staphaoffset static phase offset of the pll outputs 120 120 120 ps t outjitter pll output jitter (2) note 1 t outduty pll output clock duty cycle precision (3) 150 200 200 ps t lockmax pll maximum lock time (4) 100 100 100 s f outmax pll maximum output frequency for lx20t devices n/a 667 600 mhz pll maximum output frequency for lx30, lx30t, lx50, lx50t, lx85, lx85t, lx110, lx110t, sx35t, sx50t, fx30t, and fx70tdevices 710 667 600 mhz pll maximum output frequency for lx155, lx155t, and fx100t devices 650 600 550 mhz pll maximum output frequency for fx130t devices 550 500 450 mhz pll maximum output frequency for lx220, lx220t, lx330, lx330t, sx95t, sx240t, tx150t, tx240t, and fx200t devices n/a 500 450 mhz f outmin pll minimum output frequency (5) 3.125 3.125 3.125 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width 5 5 5 ns f pfdmax maximum frequency at the phase frequency detector 550 500 450 mhz f pfdmin minimum frequency at the phase frequency detector 19 19 19 mhz t fbdelay maximum external delay in the feedback path 3 ns max or one clkin cycle notes: 1. the pll does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequenc ies. 2. values for this parameter are available in the architecture wizard. 3. includes global clock buffer. 4. the lock signal must be sampled after t lockmax . the lock signal is invalid after configuration or reset until the t lockmax time has expired. 5. calculated as f vco /128 assuming output duty cycle is 50%.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 56 ta bl e 7 5 : pll in pmcd mode switching characteristics symbol description speed grade units -3 -2 -1 t pllcck_rel /t pllckc_rel rel setup and hold for all outputs 0.00 0.60 0.00 0.60 0.00 0.60 ns t pllccko maximum clock propagation delay 4.6 4.6 5.2 ns clkin_freq_max maximum input frequency 710 710 645 mhz clkin_freq_min minimum input frequency 1 1 1 mhz clkin_duty_cycle allowable input duty cycle: 1?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % res_rel_pulse_min minimum pulse width for rst and rel 5 5 5 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 57 dcm switching characteristics ta bl e 7 6 : operating frequency ranges for dcm in maximum speed (ms) mode symbol description speed grade units -3 -2 -1 outputs clocks (low frequency mode) f 1xlfmsmin clk0, clk90, clk180, clk270 32.00 32.00 32.00 mhz f 1xlfmsmax 150.00 135.00 120.00 mhz f 2xlfmsmin clk2x, clk2x180 64.00 64.00 64.00 mhz f 2xlfmsmax 300.00 270.00 240.00 mhz f dvlfmsmin clkdv 2.0 2.0 2.0 mhz f dvlfmsmax 100.00 90.00 80.00 mhz f fxlfmsmin clkfx, clkfx180 32.00 32.00 32.00 mhz f fxlfmsmax 180.00 160.00 140.00 mhz input clocks (low frequency mode) f dlllfmsmin clkin (using dll outputs) (1, 3, 4) 32.00 32.00 32.00 mhz f dlllfmsmax 150.00 135.00 120.00 mhz f clkinlffxmsmin clkin (using dfs outputs only) (2, 3, 4) 1.00 1.00 1.00 mhz f clkinlffxmsmax 180.00 160.00 140.00 mhz f psclklfmsmin psclk 1.00 1.00 1.00 khz f psclklfmsmax 550.00 500.00 450.00 mhz outputs clocks (high frequency mode) f 1xhfmsmin clk0, clk90, clk180, clk270 120.00 120.00 120.00 mhz f 1xhfmsmax 550.00 500.00 450.00 mhz f 2xhfmsmin clk2x, clk2x180 240.00 240.00 240.00 mhz f 2xhfmsmax 550.00 500.00 450.00 mhz f dvhfmsmin clkdv 7.5 7.5 7.5 mhz f dvhfmsmax 366.67 333.34 300.00 mhz f fxhfmsmin clkfx, clkfx180 140.00 140.00 140.00 mhz f fxhfmsmax 400.00 375.00 350.00 mhz input clocks (high frequency mode) f dllhfmsmin clkin (using dll outputs) (1, 3, 4) 120.00 120.00 120.00 mhz f dllhfmsmax 550.00 500.00 450.00 mhz f clkinhffxmsmin clkin (using dfs outputs only) (2, 3, 4) 25.00 25.00 25.00 mhz f clkinhffxmsmax 400.00 375.00 350.00 mhz f psclkhfmsmin psclk 1.00 1.00 1.00 khz f psclkhfmsmax 550.00 500.00 450.00 mhz notes: 1. dll outputs are used in these instances to describe the output s: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. other resources can limit the maximum input frequency. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by_2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45).
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 58 ta bl e 7 7 : operating frequency ranges for dcm in maximum range (mr) mode symbol description speed grade units -3 -2 -1 outputs clocks (low frequency mode) f 1xmrmin clk0, clk90, clk180, clk270 19.00 19.00 19.00 mhz f 1xmrmax 32.00 32.00 32.00 mhz f 2xmrmin clk2x, clk2x180 38.00 38.00 38.00 mhz f 2xmrmax 64.00 64.00 64.00 mhz f dllmrmin clkdv 1.191.191.19mhz f dllmrmax 21.34 21.34 21.34 mhz f fxmrmin clkfx, clkfx180 19.00 19.00 19.00 mhz f fxmrmax 40.00 40.00 40.00 mhz input clocks (low frequency mode) f clkindllmrmin clkin (using dll outputs) (1, 3, 4) 19.00 19.00 19.00 mhz f clkindllmrmax 32.00 32.00 32.00 mhz f clkinfxmrmin clkin (using dfs outputs only) (2, 3, 4) 1.00 1.00 1.00 mhz f clkinfxmrmax 40.00 40.00 40.00 mhz f psclkmrmin psclk 1.00 1.00 1.00 khz f psclkmrmax 300.00 270.00 240.00 mhz notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. when using the dcms clkin_divide_by_2 attribute these values should be doubled. other resources can limit the maximum input frequency. 4. when using a clkin frequency > 400 mhz and the dcms clkin_divide_by_2 attribute, the clkin duty cycle must be within 5% (45/5 5 to 55/45).
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 59 ta bl e 7 8 : input clock tolerances symbol description frequency range value units duty cycle input tolerance (in %) t dutycycrange_1 psclk only < 1 mhz 25 - 75 % t dutycycrange_1_50 psclk and clkin 1 - 50 mhz 25 - 75 % t dutycycrange_50_100 50 - 100 mhz 30 - 70 % t dutycycrange_100_200 100 - 200 mhz 40 - 60 % t dutycycrange_200_400 200 - 400 mhz (4) 45 - 55 % t dutycycrange_400 > 400 mhz 45 - 55 % input clock cycle-cycle jitter (low frequency mode) speed grade units -3 -2 -1 t cyclfdll clkin (using dll outputs) (1) 300.00 300.00 345.00 ps t cyclffx clkin (using dfs outputs) (2) 300.00 300.00 345.00 ps input clock cycle-cycle jitter (high frequency mode) t cychfdll clkin (using dll outputs) (1) 150.00 150.00 173.00 ps t cychffx clkin (using dfs outputs) (2) 150.00 150.00 173.00 ps input clock period jitter (low frequency mode) t perlfdll clkin (using dll outputs) (1) 1.00 1.00 1.15 ns t perlffx clkin (using dfs outputs) (2) 1.00 1.00 1.15 ns input clock period jitter (high frequency mode) t perhfdll clkin (using dll outputs) (1) 1.00 1.00 1.15 ns t perhffx clkin (using dfs outputs) (2) 1.00 1.00 1.15 ns feedback clock path delay variation t clkfb_delay_var clkfb off-chip feedback 1.00 1.00 1.15 ns notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. 3. if both dll and dfs outputs are used, follow the more restrictive specifications. 4. this duty cycle specification does not apply to the gtp_dual to dcm or gtx_dual to dcm connection. the gtp transceivers drive the dcms at the following frequencies: 320 mhz for -1 speed grade devices, 375 mhz for -2 speed grade devices, or 375 mhz for -3 speed grade devices. the gtx transceivers drive the dcms at the following frequencies: 450 mhz for -1 speed grade devices or 500 mhz fo r -2 speed grade devices.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 60 output clock jitter output clock phase alignment ta bl e 7 9 : output clock jitter symbol description constraints speed grade units -3 -2 -1 clock synthesis period jitter t perjitt_0 clk0 120 120 120 ps t perjitt_90 clk90 120 120 120 ps t perjitt_180 clk180 120 120 120 ps t perjitt_270 clk270 120 120 120 ps t perjitt_2x clk2x, clk2x180 200 200 230 ps t perjitt_dv1 clkdv (integer division) 150 150 180 ps t perjitt_dv2 clkdv (non-integer division) 300 300 345 ps t perjitt_fx clkfx, clkfx180 note 1 note 1 note 1 ps notes: 1. values for this parameter are available in the architecture wizard. ta bl e 8 0 : output clock phase alignment symbol description constraints speed grade units -3 -2 -1 phase offset between clkin and clkfb t in_fb_offset clkin/clkfb 50 50 60 ps phase offset between any dcm outputs (1) t out_offset_1x clk0, clk90, clk180, clk270 140 140 160 ps t out_offset_2x clk2x, clk2x180, clkdv 150 150 200 ps t out_offset_fx clkfx, clkfx180 160 160 220 ps duty cycle precision (2) t duty_cyc_dll dll outputs (3) 150 150 180 ps t duty_cyc_fx dfs outputs (4) 150 150 180 ps notes: 1. all phase offsets are in respect to group clk1x. 2. clkout_duty_cycle_dll applies to the 1x clock outputs (clk0, clk90, clk 180, and clk270) only if duty_cycle_correctio n = true. the duty cycle distortion includes the global clock tree (bufg). 3. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 4. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 61 ta bl e 8 1 : miscellaneous timing parameters symbol description speed grade -3 -2 -1 units time required to achieve lock t dll_240 dll output ? frequency range > 240 mhz (1) 80.00 80.00 80.00 s t dll_120_240 dll output ? frequency range 120 - 240 mhz (1) 250.00 250.00 250.00 s t dll_60_120 dll output ? frequency range 60 - 120 mhz (1) 900.00 900.00 900.00 s t dll_50_60 dll output ? frequency range 50 - 60 mhz (1) 1300.00 1300.00 1300.00 s t dll_40_50 dll output ? frequency range 40 - 50 mhz (1) 2000.00 2000.00 2000.00 s t dll_30_40 dll output ? frequency range 30 - 40 mhz (1) 3600.00 3600.00 3600.00 s t dll_24_30 dll output ? frequency range 24 - 30 mhz (1) 5000.00 5000.00 5000.00 s t dll_30 dll output ? frequency range < 30 mhz (1) 5000.00 5000.00 5000.00 s t fx_min dfs outputs (2) 10.00 10.00 10.00 ms t fx_max 10.00 10.00 10.00 ms t dll_fine_shift multiplication factor for dll lock time with fine shift 2.00 2.00 2.00 fine phase shifting t range_ms absolute shifting range in maximum speed mode 7.00 7.00 7.00 ns t range_mr absolute shifting range in maximum range mode 10.00 10.00 10.00 ns delay lines t tap_ms_min tap delay resolution (min) in maximum speed mode 7.00 7.00 7.00 ps t tap_ms_max tap delay resolution (max) in maximum speed mode 30.00 30.00 30.00 ps t tap_mr_min tap delay resolution (min) in maximum range mode 10.00 10.00 10.00 ps t tap_mr_max tap delay resolution (max) in maximum range mode 40.00 40.00 40.00 ps notes: 1. dll outputs are used in these instances to describe the outputs: clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv. 2. dfs outputs are used in these instances to describe the outputs: clkfx and clkfx180. ta bl e 8 2 : frequency synthesis attribute min max clkfx_multiply 2 33 clkfx_divide 1 32 ta bl e 8 3 : dcm switching characteristics symbol description speed grade units -3 -2 -1 t dmcck_psen / t dmckc_psen psen setup/hold 1.20 0.00 1.35 0.00 1.56 0.00 ns t dmcck_psincdec / t dmckc_psincdec psincdec setup/hold 1.20 0.00 1.35 0.00 1.56 0.00 ns t dmcko_psdone clock to out of psdone 1.00 1.12 1.30 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 62 virtex-5 device pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 8 4 . values are expressed in nanoseconds unless otherwise noted. ta bl e 8 4 : global clock input to output delay without dcm or pll symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, without dcm or pll t ickof global clock and outff without dcm or pll xc5vlx20t n/a 5.98 6.69 ns xc5vlx30 5.54 6.04 6.73 ns xc5vlx30t 5.54 6.04 6.73 ns xc5vlx50 5.59 6.09 6.79 ns xc5vlx50t 5.59 6.09 6.79 ns xc5vlx85 5.78 6.28 6.99 ns xc5vlx85t 5.78 6.28 6.99 ns XC5VLX110 5.84 6.35 7.06 ns XC5VLX110t 5.84 6.35 7.06 ns xc5vlx155 6.16 6.68 7.52 ns xc5vlx155t 6.16 6.68 7.52 ns xc5vlx220 n/a 6.99 7.71 ns xc5vlx220t n/a 6.99 7.71 ns xc5vlx330 n/a 7.17 7.91 ns xc5vlx330t n/a 7.17 7.91 ns xc5vsx35t 5.72 6.22 6.92 ns xc5vsx50t 5.77 6.27 6.97 ns xc5vsx95t n/a 6.59 7.30 ns xc5vsx240t n/a 7.24 7.98 ns xc5vtx150t n/a 6.58 7.30 ns xc5vtx240t n/a 6.88 7.61 ns xc5vfx30t 5.73 6.21 6.89 ns xc5vfx70t 5.82 6.33 7.04 ns xc5vfx100t 6.21 6.73 7.44 ns xc5vfx130t 6.28 6.80 7.52 ns xc5vfx200t n/a 7.17 7.91 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 63 ta bl e 8 5 : global clock input to output delay with dcm in system-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm in system-synchronous mode t ickofdcm global clock and outff with dcm xc5vlx20t n/a 2.53 2.93 ns xc5vlx30 2.33 2.56 2.93 ns xc5vlx30t 2.33 2.56 2.93 ns xc5vlx50 2.35 2.58 2.95 ns xc5vlx50t 2.35 2.58 2.95 ns xc5vlx85 2.41 2.63 3.00 ns xc5vlx85t 2.41 2.63 3.00 ns XC5VLX110 2.46 2.69 3.06 ns XC5VLX110t 2.46 2.69 3.06 ns xc5vlx155 2.51 2.74 3.10 ns xc5vlx155t 2.51 2.74 3.10 ns xc5vlx220 n/a 2.83 3.18 ns xc5vlx220t n/a 2.83 3.18 ns xc5vlx330 n/a 3.00 3.37 ns xc5vlx330t n/a 3.00 3.37 ns xc5vsx35t 2.44 2.67 3.03 ns xc5vsx50t 2.46 2.69 3.05 ns xc5vsx95t n/a 2.64 3.00 ns xc5vsx240t n/a 3.00 3.36 ns xc5vtx150t n/a 2.77 3.15 ns xc5vtx240t n/a 2.78 3.15 ns xc5vfx30t 2.55 2.82 3.20 ns xc5vfx70t 2.48 2.74 3.12 ns xc5vfx100t 2.33 2.59 3.00 ns xc5vfx130t 2.40 2.67 3.07 ns xc5vfx200t n/a 2.87 3.27 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 64 ta bl e 8 6 : global clock input to output delay with dcm in source-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm in source-synchronous mode t ickofdcm_0 global clock and outff with dcm xc5vlx20t n/a 3.74 4.20 ns xc5vlx30 3.45 3.71 4.15 ns xc5vlx30t 3.45 3.71 4.15 ns xc5vlx50 3.47 3.73 4.17 ns xc5vlx50t 3.47 3.73 4.17 ns xc5vlx85 3.60 3.86 4.29 ns xc5vlx85t 3.60 3.86 4.29 ns XC5VLX110 3.65 3.92 4.36 ns XC5VLX110t 3.65 3.92 4.36 ns xc5vlx155 3.91 4.18 4.62 ns xc5vlx155t 3.91 4.18 4.62 ns xc5vlx220 n/a 4.41 4.85 ns xc5vlx220t n/a 4.41 4.85 ns xc5vlx330 n/a 4.58 5.04 ns xc5vlx330t n/a 4.58 5.04 ns xc5vsx35t 3.63 3.89 4.33 ns xc5vsx50t 3.65 3.91 4.35 ns xc5vsx95t n/a 4.16 4.59 ns xc5vsx240t n/a 4.65 5.11 ns xc5vtx150t n/a 4.07 4.51 ns xc5vtx240t n/a 4.30 4.74 ns xc5vfx30t 3.74 4.05 4.50 ns xc5vfx70t 3.67 3.96 4.41 ns xc5vfx100t 3.82 4.10 4.53 ns xc5vfx130t 3.99 4.29 4.74 ns xc5vfx200t n/a 4.60 5.03 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm output jitter is already included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 65 ta bl e 8 7 : global clock input to output delay with pll in system-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay using output flip-flop, 12ma, fast slew rate, with pll in system-synchronous mode t ickofpll global clock and outff with pll xc5vlx20t n/a 2.36 2.73 ns xc5vlx30 2.03 2.30 2.70 ns xc5vlx30t 2.03 2.30 2.70 ns xc5vlx50 2.20 2.47 2.86 ns xc5vlx50t 2.20 2.47 2.86 ns xc5vlx85 2.21 2.49 2.88 ns xc5vlx85t 2.21 2.49 2.88 ns XC5VLX110 2.25 2.53 2.92 ns XC5VLX110t 2.25 2.53 2.92 ns xc5vlx155 2.34 2.60 3.01 ns xc5vlx155t 2.34 2.60 3.01 ns xc5vlx220 n/a 2.74 3.12 ns xc5vlx220t n/a 2.74 3.12 ns xc5vlx330 n/a 2.89 3.27 ns xc5vlx330t n/a 2.89 3.27 ns xc5vsx35t 2.02 2.28 2.62 ns xc5vsx50t 2.12 2.36 2.76 ns xc5vsx95t n/a 2.29 2.69 ns xc5vsx240t n/a 2.96 3.34 ns xc5vtx150t n/a 2.54 2.92 ns xc5vtx240t n/a 2.67 3.04 ns xc5vfx30t 2.44 2.67 3.06 ns xc5vfx70t 2.48 2.71 3.10 ns xc5vfx100t 2.41 2.70 3.10 ns xc5vfx130t 2.48 2.75 3.17 ns xc5vfx200t n/a 2.96 3.35 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 66 ta bl e 8 8 : global clock input to output delay with pll in source-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with pll in source-synchronous mode t ickofpll_0 global clock and outff with pll xc5vlx20t n/a 4.31 4.88 ns xc5vlx30 3.96 4.32 4.82 ns xc5vlx30t 3.96 4.32 4.82 ns xc5vlx50 4.05 4.40 4.91 ns xc5vlx50t 4.05 4.40 4.91 ns xc5vlx85 4.07 4.40 4.88 ns xc5vlx85t 4.07 4.40 4.88 ns XC5VLX110 4.11 4.44 4.92 ns XC5VLX110t 4.11 4.44 4.92 ns xc5vlx155 4.31 4.66 5.16 ns xc5vlx155t 4.31 4.66 5.16 ns xc5vlx220 n/a 4.85 5.29 ns xc5vlx220t n/a 4.85 5.29 ns xc5vlx330 n/a 5.00 5.44 ns xc5vlx330t n/a 5.00 5.44 ns xc5vsx35t 4.19 4.54 5.03 ns xc5vsx50t 4.20 4.54 5.02 ns xc5vsx95t n/a 4.68 5.14 ns xc5vsx240t n/a 5.07 5.51 ns xc5vtx150t n/a 4.51 4.95 ns xc5vtx240t n/a 4.71 5.14 ns xc5vfx30t 4.23 4.56 5.04 ns xc5vfx70t 4.22 4.54 5.02 ns xc5vfx100t 4.35 4.70 5.19 ns xc5vfx130t 4.49 4.86 5.40 ns xc5vfx200t n/a 5.04 5.55 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 67 ta bl e 8 9 : global clock input to output delay with dcm and pll in system-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm and pll in system-synchronous mode t ickofdcm_pll global clock and outff with dcm and pll xc5vlx20t n/a 2.45 2.84 ns xc5vlx30 2.25 2.48 2.84 ns xc5vlx30t 2.25 2.48 2.84 ns xc5vlx50 2.27 2.50 2.86 ns xc5vlx50t 2.27 2.50 2.86 ns xc5vlx85 2.33 2.55 2.91 ns xc5vlx85t 2.33 2.55 2.91 ns XC5VLX110 2.38 2.61 2.97 ns XC5VLX110t 2.38 2.61 2.97 ns xc5vlx155 2.43 2.66 3.01 ns xc5vlx155t 2.43 2.66 3.01 ns xc5vlx220 n/a 2.75 3.09 ns xc5vlx220t n/a 2.75 3.09 ns xc5vlx330 n/a 2.92 3.28 ns xc5vlx330t n/a 2.92 3.28 ns xc5vsx35t 2.36 2.59 2.94 ns xc5vsx50t 2.38 2.61 2.96 ns xc5vsx95t n/a 2.56 2.91 ns xc5vsx240t n/a 2.92 3.27 ns xc5vtx150t n/a 2.69 3.06 ns xc5vtx240t n/a 2.70 3.06 ns xc5vfx30t 2.47 2.74 3.11 ns xc5vfx70t 2.40 2.66 3.03 ns xc5vfx100t 2.25 2.51 2.91 ns xc5vfx130t 2.32 2.59 2.98 ns xc5vfx200t n/a 2.79 3.18 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are already included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 68 ta bl e 9 0 : global clock input to output delay with dcm and pll in source-synchronous mode symbol description device speed grade units -3 -2 -1 lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with dcm and pll in source-synchronous mode t ickofdcm0_pll global clock and outff with dcm and pll xc5vlx20t n/a 3.66 4.11 ns xc5vlx30 3.37 3.63 4.06 ns xc5vlx30t 3.37 3.63 4.06 ns xc5vlx50 3.39 3.65 4.08 ns xc5vlx50t 3.39 3.65 4.08 ns xc5vlx85 3.52 3.78 4.20 ns xc5vlx85t 3.52 3.78 4.20 ns XC5VLX110 3.57 3.84 4.27 ns XC5VLX110t 3.57 3.84 4.27 ns xc5vlx155 3.83 4.10 4.53 ns xc5vlx155t 3.83 4.10 4.53 ns xc5vlx220 n/a 4.33 4.76 ns xc5vlx220t n/a 4.33 4.76 ns xc5vlx330 n/a 4.50 4.95 ns xc5vlx330t n/a 4.50 4.95 ns xc5vsx35t 3.55 3.81 4.24 ns xc5vsx50t 3.57 3.83 4.26 ns xc5vsx95t n/a 4.08 4.50 ns xc5vsx240t n/a 4.57 5.02 ns xc5vtx150t n/a 3.99 4.42 ns xc5vtx240t n/a 4.22 4.65 ns xc5vfx30t 3.66 3.97 4.41 ns xc5vfx70t 3.59 3.88 4.32 ns xc5vfx100t 3.74 4.02 4.44 ns xc5vfx130t 3.91 4.21 4.65 ns xc5vfx200t n/a 4.52 4.94 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. dcm and pll output jitter are already included in the timing calculation.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 69 virtex-5 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 9 1 . values are expressed in nanoseconds unless otherwise noted. ta bl e 9 1 : global clock setup and hold without dcm or pll symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock and iff (2) without dcm or pll xc5vlx20t n/a 1.63 ?0.41 1.86 ?0.41 ns xc5vlx30 1.49 ?0.35 1.60 ?0.35 1.77 ?0.35 ns xc5vlx30t 1.49 ?0.35 1.60 ?0.35 1.76 ?0.35 ns xc5vlx50 1.48 ?0.30 1.59 ?0.30 1.76 ?0.30 ns xc5vlx50t 1.48 ?0.30 1.59 ?0.30 1.76 ?0.30 ns xc5vlx85 1.75 ?0.49 1.89 ?0.49 2.09 ?0.49 ns xc5vlx85t 1.75 ?0.49 1.89 ?0.49 2.09 ?0.49 ns XC5VLX110 1.74 ?0.43 1.88 ?0.43 2.09 ?0.43 ns XC5VLX110t 1.73 ?0.43 1.88 ?0.43 2.09 ?0.43 ns xc5vlx155 2.06 ?0.50 2.36 ?0.50 2.78 ?0.49 ns xc5vlx155t 2.06 ?0.50 2.36 ?0.50 2.78 ?0.49 ns xc5vlx220 n/a 2.57 ?0.74 2.86 ?0.74 ns xc5vlx220t n/a 2.57 ?0.74 2.86 ?0.74 ns xc5vlx330 n/a 2.55 ?0.56 2.85 ?0.56 ns xc5vlx330t n/a 2.57 ?0.56 2.86 ?0.56 ns xc5vsx35t 1.47 ?0.16 1.59 ?0.16 1.76 ?0.16 ns xc5vsx50t 1.62 ?0.31 1.74 ?0.31 1.93 ?0.31 ns xc5vsx95t n/a 2.10 ?0.44 2.32 ?0.44 ns xc5vsx240t n/a 2.01 0.18 2.28 0.18 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 70 t psfd / t phfd full delay (legacy delay or default delay) global clock and iff (2) without dcm or pll xc5vtx150t n/a 2.35 ?0.82 2.59 ?0.82 ns xc5vtx240t n/a 2.59 ?0.85 2.87 ?0.85 ns xc5vfx30t 2.05 ?0.27 2.25 ?0.27 2.57 ?0.27 ns xc5vfx70t 1.85 ?0.30 2.06 ?0.30 2.35 ?0.30 ns xc5vfx100t 2.20 ?0.42 2.38 ?0.42 2.66 ?0.42 ns xc5vfx130t 2.33 ?0.55 2.59 ?0.54 2.95 ?0.54 ns xc5vfx200t n/a 2.52 ?0.43 2.81 ?0.43 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. ta bl e 9 1 : global clock setup and hold without dcm or pll (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 71 ta bl e 9 2 : global clock setup and hold with dcm in system-synchronous mode symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcm / t phdcm no delay global clock and iff (2) with dcm in system-synchronous mode xc5vlx20t n/a 1.47 ?0.56 1.59 ?0.56 ns xc5vlx30 1.53 ?0.50 1.70 ?0.50 1.88 ?0.50 ns xc5vlx30t 1.53 ?0.50 1.70 ?0.50 1.88 ?0.50 ns xc5vlx50 1.52 ?0.48 1.68 ?0.48 1.86 ?0.48 ns xc5vlx50t 1.52 ?0.48 1.68 ?0.48 1.86 ?0.48 ns xc5vlx85 1.58 ?0.43 1.76 ?0.43 1.95 ?0.43 ns xc5vlx85t 1.57 ?0.43 1.76 ?0.43 1.95 ?0.43 ns XC5VLX110 1.58 ?0.37 1.76 ?0.37 1.95 ?0.37 ns XC5VLX110t 1.58 ?0.37 1.76 ?0.37 1.95 ?0.37 ns xc5vlx155 2.02 ?0.32 2.16 ?0.32 2.38 ?0.32 ns xc5vlx155t 2.02 ?0.32 2.16 ?0.32 2.38 ?0.32 ns xc5vlx220 n/a 2.17 ?0.27 2.44 ?0.27 ns xc5vlx220t n/a 2.17 ?0.27 2.44 ?0.27 ns xc5vlx330 n/a 2.17 ?0.10 2.44 ?0.10 ns xc5vlx330t n/a 2.17 ?0.10 2.44 ?0.10 ns xc5vsx35t 1.60 ?0.39 1.78 ?0.39 1.98 ?0.39 ns xc5vsx50t 1.58 ?0.37 1.76 ?0.37 1.95 ?0.37 ns xc5vsx95t n/a 2.34 ?0.41 2.35 ?0.41 ns xc5vsx240t n/a 2.25 ?0.10 2.54 ?0.10 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 72 t psdcm / t phdcm no delay global clock and iff (2) with dcm in system-synchronous mode xc5vtx150t n/a 1.85 ?0.33 2.05 ?0.33 ns xc5vtx240t n/a 2.11 ?0.32 2.35 ?0.32 ns xc5vfx30t 1.80 ?0.28 1.89 ?0.28 2.02 ?0.28 ns xc5vfx70t 1.76 ?0.36 1.86 ?0.36 1.98 ?0.36 ns xc5vfx100t 2.27 ?0.51 2.35 ?0.51 2.49 ?0.49 ns xc5vfx130t 2.33 ?0.43 2.48 ?0.43 2.72 ?0.42 ns xc5vfx200t n/a 2.30 ?0.23 2.43 ?0.21 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include dcm clk0 jitt er. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 9 2 : global clock setup and hold with dcm in system-synchronous mode (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 73 ta bl e 9 3 : global clock setup and hold with dcm in source-synchronous mode symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcm0 / t phdcm0 no delay global clock and iff (2) with dcm in source-synchronous mode xc5vlx20t n/a 0.12 0.64 0.14 0.72 ns xc5vlx30 0.27 0.62 0.27 0.62 0.27 0.66 ns xc5vlx30t 0.27 0.62 0.27 0.62 0.27 0.66 ns xc5vlx50 0.26 0.64 0.26 0.64 0.26 0.68 ns xc5vlx50t 0.25 0.64 0.26 0.64 0.26 0.68 ns xc5vlx85 0.23 0.76 0.24 0.76 0.24 0.80 ns xc5vlx85t 0.23 0.76 0.24 0.76 0.24 0.80 ns XC5VLX110 0.23 0.82 0.24 0.82 0.24 0.87 ns XC5VLX110t 0.23 0.82 0.24 0.82 0.24 0.87 ns xc5vlx155 0.12 1.08 0.14 1.08 0.16 1.13 ns xc5vlx155t 0.12 1.08 0.14 1.08 0.16 1.13 ns xc5vlx220 n/a 0.21 1.31 0.22 1.36 ns xc5vlx220t n/a 0.21 1.31 0.22 1.36 ns xc5vlx330 n/a 0.21 1.48 0.22 1.55 ns xc5vlx330t n/a 0.21 1.48 0.22 1.55 ns xc5vsx35t 0.25 0.80 0.27 0.80 0.27 0.84 ns xc5vsx50t 0.24 0.82 0.25 0.82 0.25 0.86 ns xc5vsx95t n/a 0.24 1.06 0.24 1.11 ns xc5vsx240t n/a 0.20 1.55 0.21 1.62 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 74 t psdcm0 / t phdcm0 no delay global clock and iff (2) with dcm in source-synchronous mode xc5vtx150t n/a 0.25 0.97 0.25 1.03 ns xc5vtx240t n/a 0.24 1.20 0.24 1.26 ns xc5vfx30t 0.16 0.91 0.18 0.95 0.19 1.01 ns xc5vfx70t 0.13 0.83 0.14 0.86 0.14 0.92 ns xc5vfx100t 0.21 0.98 0.21 1.00 0.21 1.05 ns xc5vfx130t 0.19 1.15 0.21 1.19 0.24 1.25 ns xc5vfx200t n/a 0.14 1.50 0.16 1.55 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include dcm clk0 jitt er. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 9 3 : global clock setup and hold with dcm in source-synchronous mode (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 75 ta bl e 9 4 : global clock setup and hold with pll in system-synchronous mode symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t pspll / t phpll no delay global clock and iff (2) with pll in system-synchronous mode xc5vlx20t n/a 1.74 ?0.82 2.02 ?0.82 ns xc5vlx30 1.53 ?0.80 1.68 ?0.80 1.90 ?0.79 ns xc5vlx30t 1.52 ?0.80 1.68 ?0.80 1.90 ?0.79 ns xc5vlx50 1.50 ?0.64 1.65 ?0.63 1.89 ?0.62 ns xc5vlx50t 1.50 ?0.64 1.65 ?0.63 1.89 ?0.62 ns xc5vlx85 1.83 ?0.63 1.95 ?0.62 2.09 ?0.61 ns xc5vlx85t 1.83 ?0.63 1.95 ?0.62 2.09 ?0.61 ns XC5VLX110 1.83 ?0.58 1.96 ?0.57 2.10 ?0.57 ns XC5VLX110t 1.83 ?0.58 1.96 ?0.57 2.10 ?0.57 ns xc5vlx155 1.91 ?0.49 2.09 ?0.49 2.37 ?0.47 ns xc5vlx155t 1.91 ?0.49 2.09 ?0.49 2.37 ?0.47 ns xc5vlx220 n/a 1.93 ?0.36 2.09 ?0.36 ns xc5vlx220t n/a 1.93 ?0.36 2.09 ?0.36 ns xc5vlx330 n/a 2.09 ?0.21 2.33 ?0.21 ns xc5vlx330t n/a 2.12 ?0.21 2.34 ?0.21 ns xc5vsx35t 1.82 ?0.82 2.02 ?0.82 2.33 ?0.82 ns xc5vsx50t 1.96 ?0.72 2.07 ?0.72 2.20 ?0.72 ns xc5vsx95t n/a 2.17 ?0.80 2.35 ?0.79 ns xc5vsx240t n/a 2.11 ?0.14 2.33 ?0.14 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 76 t pspll / t phpll no delay global clock and iff (2) with pll in system-synchronous mode xc5vtx150t n/a 1.82 ?0.56 1.95 ?0.56 ns xc5vtx240t n/a 2.05 ?0.43 2.26 ?0.43 ns xc5vfx30t 1.82 ?0.40 1.93 ?0.40 2.09 ?0.40 ns xc5vfx70t 1.79 ?0.30 1.90 ?0.30 2.07 ?0.30 ns xc5vfx100t 1.81 ?0.43 1.91 ?0.40 2.09 ?0.38 ns xc5vfx130t 1.79 ?0.29 1.95 ?0.28 2.14 ?0.24 ns xc5vfx200t n/a 2.06 ?0.14 2.29 ?0.14 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 j itter. 2. iff = input flip-flop or latch. 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 9 4 : global clock setup and hold with pll in system-synchronous mode (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 77 ta bl e 9 5 : global clock setup and hold with pll in source-synchronous mode symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t pspll0 / t phpll0 no delay global clock and iff (2) with pll in source-synchronous mode xc5vlx20t n/a ?0.26 1.21 ?0.25 1.40 ns xc5vlx30 ?0.33 1.13 ?0.33 1.22 ?0.33 1.34 ns xc5vlx30t ?0.33 1.13 ?0.33 1.22 ?0.33 1.34 ns xc5vlx50 ?0.24 1.21 ?0.24 1.30 ?0.23 1.42 ns xc5vlx50t ?0.24 1.21 ?0.24 1.30 ?0.23 1.42 ns xc5vlx85 ?0.25 1.23 ?0.23 1.30 ?0.22 1.39 ns xc5vlx85t ?0.25 1.23 ?0.23 1.30 ?0.22 1.39 ns XC5VLX110 ?0.26 1.27 ?0.24 1.34 ?0.23 1.43 ns XC5VLX110t ?0.26 1.27 ?0.25 1.34 ?0.23 1.43 ns xc5vlx155 ?0.15 1.48 ?0.12 1.56 ?0.10 1.67 ns xc5vlx155t ?0.16 1.48 ?0.12 1.56 ?0.10 1.67 ns xc5vlx220 n/a ?0.34 1.75 ?0.30 1.80 ns xc5vlx220t n/a ?0.34 1.75 ?0.31 1.80 ns xc5vlx330 n/a ?0.34 1.90 ?0.30 1.95 ns xc5vlx330t n/a ?0.34 1.90 ?0.30 1.95 ns xc5vsx35t ?0.19 1.36 ?0.18 1.44 ?0.16 1.54 ns xc5vsx50t ?0.27 1.37 ?0.26 1.44 ?0.25 1.53 ns xc5vsx95t n/a ?0.26 1.58 ?0.24 1.65 ns xc5vsx240t n/a ?0.35 1.97 ?0.31 2.02 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 78 t pspll0 / t phpll0 no delay global clock and iff (2) with pll in source-synchronous mode xc5vtx150t n/a ?0.31 1.41 ?0.29 1.47 ns xc5vtx240t n/a ?0.31 1.61 ?0.29 1.66 ns xc5vfx30t ?0.10 1.40 ?0.09 1.46 ?0.08 1.55 ns xc5vfx70t ?0.12 1.38 ?0.10 1.44 ?0.09 1.53 ns xc5vfx100t ?0.18 1.51 ?0.18 1.60 ?0.18 1.71 ns xc5vfx130t ?0.12 1.66 ?0.11 1.76 ?0.09 1.92 ns xc5vfx200t n/a ?0.12 1.94 ?0.10 2.06 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include pll clkout0 j itter. 2. iff = input flip-flop or latch. 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 9 5 : global clock setup and hold with pll in source-synchronous mode (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 79 ta bl e 9 6 : global clock setup and hold with dcm and pll in system-synchronous mode symbol description device speed grade units -3 -2 -1 input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psdcmpll / t phdcmpll no delay global clock and iff (2) with dcm and pll in system-synchronous mode xc5vlx20t n/a 1.67 ?0.64 1.78 ?0.64 ns xc5vlx30 1.72 ?0.58 1.89 ?0.58 2.07 ?0.58 ns xc5vlx30t 1.72 ?0.58 1.89 ?0.58 2.06 ?0.58 ns xc5vlx50 1.69 ?0.56 1.86 ?0.56 2.04 ?0.56 ns xc5vlx50t 1.69 ?0.56 1.86 ?0.56 2.04 ?0.56 ns xc5vlx85 1.74 ?0.51 1.93 ?0.51 2.13 ?0.51 ns xc5vlx85t 1.74 ?0.51 1.93 ?0.51 2.13 ?0.51 ns XC5VLX110 1.73 ?0.45 1.93 ?0.45 2.13 ?0.45 ns XC5VLX110t 1.73 ?0.45 1.93 ?0.45 2.13 ?0.45 ns xc5vlx155 2.14 ?0.40 2.31 ?0.40 2.55 ?0.40 ns xc5vlx155t 2.14 ?0.40 2.31 ?0.40 2.55 ?0.40 ns xc5vlx220 n/a 2.32 ?0.35 2.61 ?0.35 ns xc5vlx220t n/a 2.32 ?0.35 2.61 ?0.35 ns xc5vlx330 n/a 2.29 ?0.18 2.60 ?0.18 ns xc5vlx330t n/a 2.32 ?0.18 2.61 ?0.18 ns xc5vsx35t 1.78 ?0.47 1.97 ?0.47 2.16 ?0.47 ns xc5vsx50t 1.76 ?0.45 1.94 ?0.45 2.14 ?0.45 ns xc5vsx95t n/a 2.51 ?0.49 2.53 ?0.49 ns xc5vsx240t n/a 2.39 ?0.18 2.70 ?0.18 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 80 t psdcmpll / t phdcmpll no delay global clock and iff (2) with dcm and pll in system-synchronous mode xc5vtx150t n/a 2.00 ?0.41 2.22 ?0.41 ns xc5vtx240t n/a 2.25 ?0.40 2.51 ?0.40 ns xc5vfx30t 1.97 ?0.36 2.08 ?0.36 2.21 ?0.36 ns xc5vfx70t 1.92 ?0.44 2.03 ?0.44 2.16 ?0.44 ns xc5vfx100t 2.40 ?0.59 2.51 ?0.59 2.66 ?0.58 ns xc5vfx130t 2.46 ?0.51 2.64 ?0.51 2.89 ?0.51 ns xc5vfx200t n/a 2.44 ?0.31 2.59 ?0.30 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. these measurements include cmt jitter; d cm clk0 driving pll, pll clkout0 driving bufg. 2. iff = input flip-flop or latch. 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 9 6 : global clock setup and hold with dcm and pll in system-synchronous mode (cont?d) symbol description device speed grade units -3 -2 -1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 81 ta bl e 9 7 : global clock setup and hold with dcm and pll in source-synchronous mode symbol description device speed grade units - 3 - 2 - 1 example data input setup and hold times relative to a forwarded clock input pin, (1) using dcm, pll, and global clock buffer. for situations where clock and data inputs conform to different st andards, adjust the setup and hold values accordingly using the v alues shown in iob switching characteristics, page 32 . t psdcmpll_0 / t phdcmpll_0 no delay global clock and iff (2) with dcm and pll in source-synchronous mode xc5vlx20t n/a 0.32 0.56 0.33 0.63 ns xc5vlx30 0.45 0.54 0.46 0.54 0.46 0.57 ns xc5vlx30t 0.45 0.54 0.46 0.54 0.46 0.57 ns xc5vlx50 0.43 0.56 0.44 0.56 0.44 0.59 ns xc5vlx50t 0.43 0.56 0.44 0.56 0.44 0.59 ns xc5vlx85 0.40 0.68 0.42 0.68 0.42 0.71 ns xc5vlx85t 0.39 0.68 0.42 0.68 0.42 0.71 ns XC5VLX110 0.38 0.74 0.41 0.74 0.41 0.78 ns XC5VLX110t 0.38 0.74 0.41 0.74 0.41 0.78 ns xc5vlx155 0.24 1.00 0.29 1.00 0.33 1.04 ns xc5vlx155t 0.24 1.00 0.29 1.00 0.33 1.04 ns xc5vlx220 n/a 0.36 1.23 0.38 1.27 ns xc5vlx220t n/a 0.36 1.23 0.38 1.27 ns xc5vlx330 n/a 0.34 1.40 0.37 1.46 ns xc5vlx330t n/a 0.36 1.40 0.38 1.46 ns xc5vsx35t 0.44 0.72 0.46 0.72 0.46 0.75 ns xc5vsx50t 0.41 0.74 0.43 0.74 0.43 0.77 ns xc5vsx95t n/a 0.41 0.98 0.41 1.02 ns xc5vsx240t n/a 0.35 1.47 0.38 1.53 ns
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 82 t psdcmpll_0 / t phdcmpll_0 no delay global clock and iff (2) with dcm and pll in source-synchronous mode xc5vtx150t n/a 0.40 0.89 0.40 0.94 ns xc5vtx240t n/a 0.38 1.12 0.39 1.17 ns xc5vfx30t 0.34 0.83 0.36 0.87 0.37 0.92 ns xc5vfx70t 0.29 0.75 0.32 0.78 0.32 0.83 ns xc5vfx100t 0.35 0.90 0.35 0.92 0.35 0.96 ns xc5vfx130t 0.33 1.07 0.37 1.11 0.41 1.16 ns xc5vfx200t n/a 0.29 1.42 0.33 1.46 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. the timing values were measured using th e fine-phase adjustment feature of the dcm. these measurements include cmt jitter; dcm clk0 driving pll, pll clkout0 driving bufg. package skew is not included in these measurements. 2. iff = input flip-flop. ta bl e 9 7 : global clock setup and hold with dcm and pll in source-synchronous mode symbol description device speed grade units - 3 - 2 - 1
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 83 source-synchronous switching characteristics the parameters in this section provide the necessary va lues for calculating timing budgets for virtex-5 fpga source-synchronous transmitter and receiver data-valid windows. ta bl e 9 8 : duty cycle distortion and clock-tree skew symbol description device speed grade units -3 -2 -1 t dcd_clk global clock tree du ty cycle distortion (1) all 0.12 0.12 0.12 ns t ckskew global clock tree skew (2) xc5vlx20t n/a 0.24 0.25 ns xc5vlx30 0.21 0.22 0.22 ns xc5vlx30t 0.21 0.22 0.22 ns xc5vlx50 0.26 0.27 0.28 ns xc5vlx50t 0.26 0.27 0.28 ns xc5vlx85 0.42 0.43 0.45 ns xc5vlx85t 0.42 0.43 0.45 ns XC5VLX110 0.48 0.50 0.51 ns XC5VLX110t 0.48 0.50 0.51 ns xc5vlx155 0.82 0.85 0.88 ns xc5vlx155t 0.82 0.85 0.88 ns xc5vlx220 n/a 1.07 1.10 ns xc5vlx220t n/a 1.07 1.10 ns xc5vlx330 n/a 1.25 1.29 ns xc5vlx330t n/a 1.25 1.29 ns xc5vsx35t 0.38 0.39 0.39 ns xc5vsx50t 0.43 0.44 0.45 ns xc5vsx95t n/a 0.72 0.74 ns xc5vsx240t n/a 1.32 1.36 ns xc5vtx150t n/a 0.70 0.73 ns xc5vtx240t n/a 0.97 1.00 ns xc5vfx30t 0.34 0.35 0.35 ns xc5vfx70t 0.41 0.42 0.43 ns xc5vfx100t 0.82 0.84 0.86 ns xc5vfx130t 0.82 0.84 0.86 ns xc5vfx200t n/a 1.24 1.29 ns t dcd_bufio i/o clock tree duty cycle distortion all 0.10 0.10 0.10 ns t bufioskew i/o clock tree skew across one clock region all 0.07 0.07 0.08 ns t dcd_bufr regional clock tree duty cycle distortion all 0.25 0.25 0.25 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pi ns of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to the application.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 84 ta bl e 9 9 : package skew symbol description device package value units t pkgskew package skew (1) xc5vlx20t ff323 131 ps xc5vlx30 ff324 80 ps ff676 142 ps xc5vlx30t ff323 127 ps ff665 93 ps xc5vlx50 ff324 80 ps ff676 142 ps ff1153 175 ps xc5vlx50t ff665 93 ps ff1136 162 ps xc5vlx85 ff676 142 ps ff1153 174 ps xc5vlx85t ff1136 164 ps XC5VLX110 ff676 142 ps ff1153 173 ps ff1760 190 ps XC5VLX110t ff1136 163 ps ff1738 171 ps xc5vlx155 ff1153 161 ps ff1760 181 ps xc5vlx155t ff1136 147 ps ff1738 174 ps xc5vlx220 ff1760 178 ps xc5vlx220t ff1738 156 ps xc5vlx330 ff1760 177 ps xc5vlx330t ff1738 155 ps xc5vsx35t ff665 103 ps xc5vsx50t ff665 103 ps ff1136 157 ps xc5vsx95t ff1136 176 ps xc5vsx240t ff1738 161 ps xc5vtx150t ff1156 ps xc5vtx150t ff1759 157 ps xc5vtx240t ff1759 157 ps xc5vfx30t ff665 102 ps xc5vfx70t ff665 102 ps ff1136 153 ps xc5vfx100t ff1136 144 ps ff1738 172 ps xc5vfx130t ff1738 181 ps xc5vfx200t ff1738 164 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). 2. package trace length information is available for these device/package combinations. this information can be used to deskew t he package.
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 85 revision history the following table shows the revision history for this document. table 100: sample window symbol description device speed grade units -3 -2 -1 t samp sampling error at receiver pins (1) all 450 500 550 ps t samp_bufio sampling error at receiver pins using bufio (2) all 350 400 450 ps notes: 1. this parameter indicates the total sampling error of virtex-5 fpga ddr input registers across voltage, temperature, and proce ss. the characterization methodology uses the dcm to capture the ddr input registers? edges of operation. these measurements include: - clk0 dcm jitter - dcm accuracy (phase offset) - dcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-5 fpga ddr input registers across voltage, temperature, and proce ss. the characterization methodology uses the bufi o clock network and iodelay to capture th e ddr input registers? edges of operation. t hese measurements do not include package or clock tree skew. table 101: source-synchronous pin-to-pin setup/hold and clock-to-out symbol description speed grade units -3 -2 -1 data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock ?0.56 1.59 ?0.54 1.72 ?0.54 1.91 ns pin-to-pin clock-to -out using bufio t ickofcs clock-to-out of i/o clock 4.42 4.82 5.40 ns date version revision 04/14/06 1.0 initial xilinx release. 05/12/06 1.1 ? first version posted to the xilinx website. minor typographical edits. revised design software version on page 30 . ? revised t idelayresolution in table 64, page 44 . ? revised tdspcko in table 69, page 48 . 05/24/06 1.2 added register-to-register parameters to ta b l e 5 2 . 08/04/06 1.3 ? added v drint , v dri , and c in values to ta bl e 3 . ? added hstl_i_12 and lvcmos12 to ta bl e 7 and renumbered the notes. ? removed pin-to-pin performance (table 12). updated and added values to register-register performance ta bl e 5 2 (was table 13). ? added values to ta b l e 5 3 . ? updated the speed specification version above ta bl e 5 4 . ? added to ta b l e 5 6 the i/o standards: hstl_ii_t_dci, hstl_ii_t_dci_18, sstl2_ii_t_dci, and sstl18_ii_t_dci. ? revised f max values in ta b l e 6 8 , and rdwr_b setup/hold values in ta b l e 7 0 . ?in ta b l e 7 4 , changed f vcomax , removed t lockmin , and revised t lockmax values, also removed note pointing to architecture wizard. ? removed note 2 on ta bl e 8 8 .
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 86 09/06/06 2.0 ? added new sections for lxt devices and added lx t devices to the appropriate tables. the addition of the gtp_dual tile specifications required the tables to be renumbered. ? changed maximum v in values in ta b l e 1 and ta bl e 2 . ? updated values and added t j = 85c to table 4, page 3 . ? revised the cascade block ram memory, page 28 section in ta bl e 5 2 to 64k with new i/o delays. ? revised the setup and hold times in table 60, page 40 . ? added f max_cascade to table 68, page 47 . ? revised f fxlfmsmax and f clkinlffxmsmax in table 76, page 57 . 10/13/06 2.1 ? added system moni tor parameters. added xc5vlx85t to appropriate tables. ? revised ta b l e 2 8 including notes. added ta bl e 2 9 , and figure 3 and figure 4 . ? added table 48, page 25 : rocketio crc block. ? revised design software version and ta bl e 5 4 on page 30 . ? updated ilogic switching characteristics, page 40 ? updated f max_ecc in table 68, page 47 . ? changed hold times for t smdcck / t smcckd and t bpidcc /t bpiccd in table 70, page 51 . ? revised t fbdelay , f outmin , f outmax , and f injitter table 74, page 55 . ? revised table76, page57 . 01/05/07 2.2 ? added i in to ta b l e 2 . added xc5vlx220t to appropriate tables. ? added lvdci33, lvdci2 5, lvdci18, lvdci15 to ta bl e 7 . ? update the symbols in the gtp transceiver ta b l e 2 4 , ta b l e 2 5 , and ta bl e 2 6 . ? add values for -1 speed grade in table 30, page 16 . ? added sfi-4.1 values to table 53, page 29 . ? removed -3 speed grade from available lx220 device list in table 54, page 30 . ? added maximum frequency to ta b l e 7 2 and table 73, page 54 . ?in table 76, page 57 changed the all the clkdv, clkfx, and clkfx180 min values and the clkin min values in the input clocks (high frequency mode) section. ? added values to ta b l e 7 9 and table80, page60 . date version revision
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 87 02/02/07 3.0 ? added xc5vsx35t, xc5vsx50t, and sx5vsx95t devices to appropriate tables. ? revised the i rpu values in table 3, page 2 . ? revised the i ccauxq values in table 4, page 3 . ? added values to table 5, page 6 . ? minor added notes and changed descriptions in table 25, page 13 and table 26, page 13 . ? revised the sfi-4.1 (sdr lvds interface) -1 values in table 53, page 29 . ? revised gain error, bipolar gain error, and event conversion time in table51, page26 ? changed the design software version that matches this data sheet above ta b l e 5 4 on page 30 . ?in switching characteristics , the following values are revised: ? lvcmos25, fast, 12 ma in table 56, page 32 . ? setup and hold and t ickq in table 60, page 40 . ?t ockq in table 61, page 41 . ? sequential delay values in table 63, page 43 . ?t cxb , t ceo , and t dick in table 65, page 44 . ?t rcko_do , t rcko_pointers , t rcko_eccr , t rcko_ecc , t rcck_addr , t rdck_di , t rdck_di_ecc , t rcck_wren , and t rco_flags in table 68, page 47 . ?t dspdck_cc , t dspcck_{rstaa, rstbb} , t dspcko_{pp, cryoutp} , f max_mult_nomreg and f max_mult_nomreg_patdet in table 69, page 48 . ?t bccko_o , and t bgcko_o in table 71, page 53 . ?t bufiocko_o and f max in table 72, page 53 . ?t brcko_o and t brcko_o_byp in table 73, page 54 . ? parameters in table 74, page 55 including notes. ?in virtex-5 device pin-to-pin output parameter guidelines : ? revised values in ta b l e 8 4 , ta b l e 8 5 , and ta b l e 8 6 . ?in virtex-5 device pin-to-pin input parameter guidelines : ? clarified description in table 91, page 69 . ? revised values in ta b l e 9 1 , ta b l e 9 2 , and ta b l e 9 3 . ? removed duplicate t bufr_max_freq and t bufio_max_freq from ta b l e 9 8 . ? revised values in table 101, page 85 . date version revision
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 88 05/18/07 3.1 ? added typical values for n and r in ta bl e 3 . ? revised and added values to ta b l e 4 . ? revised standard i/o levels in ta bl e 7 . ? additions and updates to ta b l e 2 6 , ta b l e 2 8 , ta b l e 2 9 , ta b l e 3 0 , ta b l e 4 8 , ta b l e 3 2 , ta bl e 3 3 , ta bl e 3 4 , and ta bl e 3 5 . ? added ethernet mac switching characteristics, page 25 . ? changed the design software version that matches this data sheet above ta b l e 5 4 on page 30 . ? added new section: i/o standard adjustment measurement methodology, page 37 . ?in switching characteristics , the following values are revised: ? lvttl, slow and fast, 2 ma, 4 ma, and 6 ma ( ta bl e 5 6 ). ? lvcmos33, slow and fast, 2 ma, 4 ma, and 6 ma ( ta b l e 5 6 ). ? lvcmos25, slow and fast, 2 ma and 4 ma, and fast 12 ma ( ta bl e 5 6 ). ? lvcmos18, slow and fast, 2 ma, 4 ma, and 6 ma ( ta b l e 5 6 ). ? lvcmos15 and lvcmos12, slow and fast, 2 ma ( ta bl e 5 6 ). ?t idock and t idockd in ta b l e 6 0 . ? setup/hold for control lines and data lines in ta b l e 6 2 . ?add t idelaypat_jit and revised t idelayresolution in table 64, page 44 and added notes 1 and 2. ? revised t rck page 45 and removed t cksr table 65, page 44 . ? replaced t twc with t mcp symbol in table 66, page 46 . ? revised t ceck in ta b l e 6 7 . ? revised t rcko_flags and t rdck_di_ecc encode only in ta bl e 6 8 . ? revised hold times of data/control pins to the input register clock. setup/hold times of {pcin, carrycascin, multsign in} input to p register clk. hold times of some of the ce pins. hold times of some of th e rst pins. hold times of {a, b} input to {p, carryout} output using multip lier and {acin, bcin} input to {p, carryout} output using multiplier, clk (areg, breg) to {p, carryout} output using multiplier, in ta bl e 6 9 . ? updated and added values to table 70, page 51 . ? revised -1 speed f max value in table 72, page 53 . ? added note 4 to t lockmax and revised f induty , f inmax ,and f vcomax in table 74, page 55 . ? added values to ta b l e 7 9 and ta b l e 8 0 . changed t out_offset in ta bl e 8 0 . ?in virtex-5 device pin-to-pin output parameter guidelines : ? revised values in ta b l e 8 4 through ta b l e 9 0 . ?in virtex-5 device pin-to-pin input parameter guidelines : ? revised values in ta b l e 9 1 through ta b l e 9 7 . ?in source-synchronous swit ching characteristics : ? revised values in table98, page83 . ? added package skew values to table 99, page 84 . ? revised values in table 101, page 85 . 06/15/07 3.2 ? updated t stg in ta bl e 1 . ? corrected v oh /v ol in ta bl e 9 and table10, page8 . ? changed the design software version that matches this data sheet above ta b l e 5 4 on page 30 . ? added production silicon and ise software status, page 31 . ? added t iodelay_clk_max and revised t cksr in table 64, page 44 . ?in virtex-5 device pin-to-pin output parameter guidelines : revised values in ta bl e 8 5 through ta b l e 9 0 . ?in virtex-5 device pin-to-pin input parameter guidelines : revised values in ta b l e 9 2 through ta b l e 9 7 . ? corrected units to ns in table 98, page 83 . date version revision
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 89 06/26/07 3.3 ? added conditions to dv ppin in table 28, page 14 . ? changed the f gtxmax symbol name to f gtpmax . ? updated gtp maximum line rates to 3.75 gb/s in table 30, page 16 . ? updated maximum frequencies in table33, page17 . ? added 3.75 gb/s condition and changed maximum value of f gtx in table 34, page 17 . ? added 3.75 gb/s sinusoidal jitter specification and changed maximum value of f grx in ta bl e 3 5 , page 18 . ? changed analog input common mode ranges in table 51, page 26 . ? changed t pkgskew values in table99, page84 . 07/26/07 3.4 ? added maximum value of i ref to table 3, page 2 . ? revised ta b l e 5 4 and changed the design software version in ta bl e 5 5 for production devices. ?in table 64, page 44 , added high performance mode to note 2. ?in table 70, page 51 , revised description of t smdcck /t smcckd . ? added note 4 to t dutycycrange_200_400 frequency range in table 78, page 59 . ?in virtex-5 device pin-to-pin input parameter guidelines : revised note 1 in ta bl e 9 1 through ta b l e 9 6 . 09/27/07 3.5 ? added i batt value and note 2 to ta bl e 3 . ? added drp clock frequency and note 4 to ta b l e 5 1 . revised the typical and maximum values and units for gain error and bipolar gain error. ? removed unsupported xc5vsx95t -3 speed grade from ta b l e 5 4 and ta b l e 5 5 . ? removed unsupported i/o standards (lvds_33, lvdsext_33, and ulvds_25) from ta b l e 5 1 . also updated lvdsext, 2.5v in ta b l e 5 9 . ? added values to dynamic reconfiguration port (drp) for dcm and pll before and after dclk in ta b l e 7 0 . ?in virtex-5 device pin-to-pin input parameter guidelines : revised note 1 in ta bl e 9 1 through ta b l e 9 7 . 11/05/07 3.6 ? removed note 1 from table 52, page 28 . f max of clock is not an applicable limitation. ? revised ddr2 memory interface performance in table53, page29 . ? revised ta b l e 5 5 to add ise 9.2i sp3 where applicable. ? removed xc5vsx95t -3 speed grade support from applicable tables. ? removed unsupported i/o standard (lvpecl_33) from ta bl e 5 8 and added lvpecl_25. ? added t smco and t smckby to table 70, page 51 . ? revised note 3 in table 76, page 57 and table77, page58 . ? clarified notes in ta b l e 8 7 to ta bl e 9 0 , and ta b l e 9 4 to ta b l e 9 7 . ? revised note 1 in ta bl e 9 9 . 12/11/07 3.7 ? added new devices (xc5vlx20t, xc 5vlx155, and xc5vlx155t) throughout document. ? removed -3 speed grade from xc5vsx95t device lists. ? added table 31, page 16 . ? revised virtex-5 device pin-to-pin output parameter guidelines in ta bl e 8 7 through ta b l e 9 0 , and virtex-5 device pin-to-pin input parameter guidelines in ta b l e 9 0 and ta bl e 9 2 through ta b l e 9 7 . also revised note 1 on ta b l e 9 2 through ta b l e 9 7 . ? revised note 1 on ta b l e 9 9 . 02/05/08 3.8 ? updated date on version 3.7. other minor typographical edits. ? updated the sentence: xilinx does not specify the current or i/o behavior for other power-on sequences, on page 6 . ? added values and notes to table 27, page 14 . removed i ccintq since it is included in table 4, page 3 . combined i vttrxcq into i vttrxq values. ? revised t llskew values in table 34, page 17 . ? revised r xppmtol values and note 1 in table 35, page 18 . ? revised -2 performance value for spi-4.2 in table 53, page 29 . ? added t ioddo_t , t ioddo_idatain , t ioddo_odatain , and note 3 to table 64, page 44 . ? split out the f max rows in ta b l e 7 1 and the f outmax rows in ta b l e 7 4 , revised -2 value for smallest devices in both tables. ? added ta bl e 7 5 : pll in pmcd mode switching characteristics, page 56 . ? updated ta b l e 4 and ta bl e 8 4 to ta bl e 9 8 to match speed grade designations listed in ta bl e 5 4 . ? revised note 1 on ta b l e 9 6 and ta b l e 9 7 . date version revision
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 90 03/31/08 4.0 ? added xc5vfx30t, xc5vfx70t, xc5vfx10 0t, xc5vfx130t, xc5vfx200t devices to appropriate tables. ? updated power-on power supply requirements, page 6 . ? added gtx_dual tile specifications and powerpc 440 switching characteristics sections. ? corrected mgtavcc in table 24, page 13 . ? updated mgtr ref in table 26, page 13 . ? changed the symbol names to f gtptx in ta b l e 3 4 and f gtprx in ta b l e 3 5 . ?moved the crc block switching characteristics to table48, page25 . ? added notes to ta b l e 5 3 . ? revised speed specification version to 1.59. 04/25/08 4.1 ? added xc5vsx240t to appropriate tables. ? clarified maximum frequency descriptions in table 68, page 47 . ? added maximum readback frequency (f rbcck ) to selectmap mode programming switching in ta b l e 7 0 . ? revised speed specification version to 1.60. 05/09/08 4.2 ? revised ethernet mac switching characteristics and added endpoint block for pci express designs switching characteristics . ? revised some v meas values and added note 6 to table58, page37 . added figure 12, page 38 to output delay measurements . revised some v meas and r ref values and added note 4 to ta b l e 5 9 , page 38 . ? reversed the order of th e setup/hold values for t pllcck_rel /t pllckc_rel in table75, page56 . ? added package skew values to table 99, page 84 . 05/15/08 4.3 ? revised table12, page9 . 06/12/08 4.4 ? added values to some devices in ta b l e 4 . ? increased the maximum v in in table 28, page 14 . ? revised v idiff and v ise in ta bl e 2 9 , figure 3 , and figure 4, page 15 . same change for gtx transceivers in ta b l e 4 1 , figure 8 , and figure 9, page 21 . ? added values to ta b l e 4 3 . ? updated ta b l e 5 4 and ta b l e 5 5 with production status on some devices. ?in ta bl e 7 1 , revised t bcck0_0 , t bgck0_0 . in ta bl e 7 3 , revised t brcko_o , and t brcko_o_byp . ? revised xc5vlx20t, xc5vlx155, xc5vlx155 t, xc5vfx30t, xc5vfx70t, xc5vfx100t, xc5vfx130t, and some xc5vsx240t values in ta b l e 8 4 through ta b l e 9 8 . 06/18/08 4.5 ? added values to ta b l e 5 . 06/26/08 4.6 ? added values to ta b l e 5 . ? moved xc5vlx20t to production in ta b l e 5 4 and ta b l e 5 5 . ? updated the f outmax in ta bl e 7 4 . 09/23/08 4.7 ? added xc5vtx150t and xc5vtx 240t devices to appropriate tables. ? added values to ta b l e 4 and ta bl e 5 . ? updated data in ta b l e 3 8 , ta b l e 3 9 , ta bl e 4 0 , ta bl e 4 1 , ta b l e 4 2 , ta b l e 4 4 , ta b l e 4 5 , ta b l e 4 6 , and ta b l e 4 7 . ? moved xc5vlx20t to production in ta b l e 5 4 and ta b l e 5 5 . ? added note 8 to table 68, page 47 . ? added note 1 to table 74, page 55 . date version revision
virtex-5 fpga data sheet: dc and switching characteristics ds202 (v5.3) may 5, 2010 www.xilinx.com product specification 91 notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein ("products") are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage ("critical applications"). use of products in critical applicat ions is at the sole risk of customer, subject to applicable laws and regulations. 12/02/08 4.8 ? added i in row to absolute maximum ratings in table1, page1 . ?in table 32, page 16 , changed duty cycl e values for t dcref and added note 2. ? changed conditions for t phase in table32, page16 and table 44, page 22 . ?in table 35, page 18 , updated r xppmtol values, updated note 1, and added note 2. ?in table 45, page 23 , updated parameters with separate fxt and txt values. ?in table 46, page 23 , corrected units of t llskew . ?in table 54, page 30 , updated sx240t, fxt, and txt speed grade designations. ?in table 55, page 31 , updated sx240t and fxt rows. ?in table 58, page 37 , added lvcmos, 1.2v row. ?in table 59, page 38 , corrected v meas value for lvcmos, 1.2v row. ?in table 80, page 60 , updated note 3 with sentence about global clock tree. 12/19/08 4.9 ? updated table 5, page 6 with power-on current values for xc5vsx240t, xc5vtx150t, xc5vtx240t, xc5vfx100t, and xc5vfx200t devices. 01/14/09 4.10 ? in table 1, page 1 , changed note 2 to refer to ug112 for soldering guidelines. ?in table 54, page 30 , moved speed grades for the xc5vtx150t and xc5vtx240t devices to production. ?in table 55, page 31 , added the ise software version for the xc5vtx150t and xc5vtx240t devices. ?in table 80, page 60 , moved the reference to the duty cycle distortion note to apply to both t duty_cyc_dll and t duty_cyc_fx . 02/06/09 5.0 ? changed document classification from advanc e product specification to product specification. ?in table 1, page 1 , changed v in and added note 5. ?in table 5, page 6 , removed the max columns and added note 2 about calculating the maximum startup current. ?in table 74, page 55 , removed lx20t from second row of f outmax . 04/01/09 5.1 ? in table 65, page 44 , changed ?a ? d input? to ?ax ? dx input? for the t dick /t ckdi parameter. ?in table 74, page 55 , prepended ?? to all speed grade values for the t outduty parameter. 06/25/09 5.2 ? in table 2, page 2 , added note 6. ?in table 11, page 9 , changed v ccaux to v cco in note 1. 05/05/10 5.3 removed dv ppin from the examples in figure 2 and figure 7 . in ta b l e 3 1 , changed ?gtpdrpclk? to ?gtp dclk (drp clock)? in the description column. in ta bl e 3 5 , added table note 2 about r xppmtol . in ta bl e 4 1 , changed the maximum value of v ise to 1000 mv. in ta bl e 4 2 , changed the minimum pll frequency (f gpllmin ) to 1.48 ghz for all three speed grades. in ta b l e 4 3 , changed ?gtxdrpclk? to ?gtx dclk (drp clock)? in the description column. in ta bl e 4 5 , removed ?2 byte or 4 byte interface? from the conditions column for t rx and t tx . in ta bl e 4 7 , added table note 2 about r xppmtol . in ta bl e 5 1 , changed the maximum value of ai dd to 13 ma. in ta bl e 7 4 , updated description of t fbdelay . date version revision

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